Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
A specific cominational function can be coded in several ways. (See examples below)
(1) Will different HDL implementations be synthesized differently?
(2) If (1) is true, are there any guidelines of which coding style is better?
for example - Find First Set
module FFS_1(input wire [2:0] i, output wire [1:0] o); assign o = (i==0)?2'bxx:(i==1)?2'b01:(i<4)?2b'10:2'b11;endmodule
module FFS_1(input wire [2:0] i, output wire [1:0] o);
assign o = (i==0)?2'bxx:(i==1)?2'b01:(i<4)?2b'10:2'b11;
module FFS_2(input wire [2:0] i, output reg [1:0] o); always @(i) begin integer j, found; found = 0; o = 2'bx; for (j=2; j>0; j=j-1) if (i[j] && !found) begin found = 1; o = j; endendmodule;
module FFS_2(input wire [2:0] i, output reg [1:0] o);
integer j, found;
found = 0;
o = 2'bx;
for (j=2; j>0; j=j-1)
if (i[j] && !found)
found = 1;
o = j;
Both modules are pure combinational logic and describe the exact same function (find first set bit with DC for input=0). Will the two have the same gate level implementation?
Of course, this is only an example of a simple function (3b-->2b) so any student can use karnaugh maps to minimize. But I can think of a much more complicated example - change the input vector to be 100 bits wide, another input indicates a cyclic shift to apply to the input vecor, and the output are the indices of the 10 first set bits. This function is much easier to describe using an always block, it's easier to code, easier to read, and easier to change in case the function has to be changed. This is a 107b-->70b function... Will both styles result with same gate level? Can I expect one coding style to be better than the other (area/timing/etc.)?
Of course, I'm only talking about the combinational parts, if I use more/less flops I won't expect same results, but my question is about the logic in between. Are there any guidelines?
Thanks in advance
Hi Tzachy Noy,
There is more to good HDL coding than functional accuracy. In the case you provided they may not even be equivalent since I am not sure you accounted for don't care conditions in the same way so its X and Z behavior may differ. I would say that the goal of every tool is to arrive at an optimal solution irrespective of input but certain constructs lend themselves better to certain optimizations. Some enable better operator merging, some enable better structuring of CSA tree, some are more immune to X and Z issues in simulation, some will simulate faster.... you get the idea.
As you indicated, once the cone of logic gets really complex, it is not unlikely that small changes in the coding style could lead to slightly different solutions. 10, 20 years ago tools were very sensitive to such changes but as tools matured they are less sensitive and closer to optimal. However, a small coding style change can still have a large impact in some cases.
Even the use of hierarchy can have an impact in how fast or slow a given tool runs. Unfortunately, learning this is part education and part experience. On the education side you can start with RTL Compiler's HDL modelling guide and you can find a number of reasonable publications thought google searches as well.
I know this is not the clear answer you were looking for but this is a topic that does not have a one-size-fits-all answer