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I would like to know how do we specify internal clock pins (output of PLL internal to design) to the CONFORML tool for doing CDC checks as the 'add clock' command accepts only primary inputs as definable clocks. The design I want to perform CDC on, has clocks as inputs to the design as well as some clocks which are generated internal to the design.
This is Jack Ho from Cadence.
In order to use the command "add clock" on an internal pin/net, you will need to use the "add primary input" command first, which essentially makes it a primary input.
The syntax for add primary input looks like this:
ADD PRimary Input
< [-Net] | -Pin>>
So your script will look something like this
add primary input PLL/output -pin
add clock ...
Having said that, we have since then introduced an improved CDC solution within our CCD (Conformal Constraint Designer) product. It performs both sdc checks and CDC checks within the same tool, providing closed-loop verification of both your timing constraints and clock domain crossings. If you are going to perform clock domain checks, you would want to, first of all, validate your clock domain definitions and groupings for a more complete solution.