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Just FYI, The Silicon Valley CDNLive! papers are available now for CDNLive! attendees.(They will become available to all in 3 months time.)Look for the "CDNLive!" tab at the top of the cdnusers.org page and the pull-down is labelled "Silicon Valley 2006 Proceedings"The URL is: http://www.cdnusers.org/CDNLive/SiliconValley2006Proceedings/tabid/366/Default.aspx(Note that the links may not work for you unless you are logged in and were a CDNLive! attendee.)Below, I have excerpted the abstracts and links to the 2 papers that I had highlighted in earlier postings:1) Session 2.4.1: Best known methods for using Cadence Conformal LEC at Intel In this presentation we will explore how to use the Cadence Conformal LEC tool capabilities to verify different types of designs. In particular, we will focus on the Conformal Ultra capability for verifying complex data-path synthesis and layout. We will use it together with the set effort 'complete' command, in order to force the Cadence Conformal LEC to compare all the aborted state points. The design we will present is a 1 Gigabit Ethernet chip with around 10 million standard cells. At first look we thought that we will need to use the divide and conquer technique and split the big design into smaller blocks in order to complete the verification. To our surprise, using the Conformal Ultra together with the effort 'complete' we managed to verify the entire design in one flat run. In this presentation we will discuss when to use the different Cadence Conformal LEC capabilities and what benefits they provide. When to use the Conformal Ultra and when not? Why you need to use the effort complete wisely? The following learning are based on using the Cadence Conformal LEC on different types of designs at Intel. This kind of information can provide a significant saving of time and increase the user productivity. We will wrap up by presenting additional tips of accelerating the design flow using the Cadence Conformal LEC.  The complexity of theorem proving procedures, S. A. Cook, Proceedings of the 3rd Annual ACM Symposium on Theory of Computing (1971), pp. 151-158.ErikSeligman, Intel The Paper is at: http://cdnusers.org/Portals/0/cdnlive/na2006/2.4.1/2.4.1_paper.pdf and the presentation is at: http://cdnusers.org/Portals/0/cdnlive/na2006/2.4.1/2.4.1_presentation.pdf2) Session 2.7: Formal and Structural Analysis of Power Management Designs Using Conformal Low Power Low power and higher performance are two crucial requirements for mobile devices. As leakage power continue to increase in smaller process nodes, power management design must address both active and leakage power. This, however, poses a significant challenge to the design verification. The verification complexity is amplified by the fact that the majority of the low-power function is introduced into the gate netlist during synthesis and physical implementation. Electrical integrity check is limitted in gate level simulation. Silicon re-spin risk due to low-power isolation functional and electrical integrity problems is real. Texas Instruments has partnered with the Cadence Conformal team to address this challenge enabling netlist level low-power isolation functional verification to identify any electrical integrity issues. This session outlines the use of Encounter Conformal Low Power in our design flow. We will describe how Conformal Low Power allows us to run structural checks to make sure low power cells are inserted and connected correctly and to formally verify isolation function in our design.LamHo, Texas Instruments The Presentation is at: http://cdnusers.org/Portals/0/cdnlive/na2006/2.7/2.7_presentation.pdfThanks!---Dave