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Tip of the Month: The dangers of using "set undriven signal" in Conformal ECSay you have a design with floating inputs that cause non-equivalencesin Conformal EC and you hear "set undriven signal" fixed a similar problemwith another design. You ask yourself, "Is this a safe method to verifymy design? Is there a better way of doing this?" set undriven signal is a Conformal EC command that globally ties allfloating signals to a defined value: set undriven signal < Z | 0 | 1 | X > [-Both | -Golden | -Revised] One has to exercise caution with global constraints. Here are twopotential pitfalls when using this command:1) The undriven signal was not intended. This can occur more easily inVHDL than in Verilog. As an example: signal one : std_logic := '1';Here the designer's obvious intent is to have a signal called 'one' tiedto a constant '1'. Yet, synthesis will tie it off to '0' since theinitial assignment (:= in VHDL) is ignored. Blindly using 'set undrivensignal 0 -golden' will cause this gross error to be covered up. The codeshould have been changed to: signal one : std_logic; [begin] one <= '1'; -- now a real driver2) If just "set undriven signal 0" is used, Conformal EC will tie floating inputsto zero in both the golden and revised (since -both is the default).This could make the non-equivalences go away but it could also mask atie-off synthesis problem. If the synthesis tool didn't tie a floatinginput to zero then the implied -both will tie RTL and gate floatinginputs to zero and report equivalence.Here are recommendations when encountering undriven signals in anRTL-to-gate run: