Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have two questions about pnoise jitter calculation in SpectreRF.
1. What is the meaning of Freq. Multiplier in jitter calculator?
2. What is the optimum integration range of phase noise for jitter calculation?
Actually, I posted about similar subject last year, but I'm still confused..... : (
I need to calculate VCO's jitter to estimate the SNR limit of synchronous ADC by clock.
I've done PSS/PNOISE simulation like following condtion
- Free running VCO
- VCO clock speed : 10MS/s
- Total ADC conversion time : 100us(1000cycle)
Beat frequency : 10MHz
Output harmonics(Number of harmonics) : 0
Output Frequency Sweep Range : 1~500MHz(I have no idea what's the right sweep range. I just think it would be wide enough)
Maximum Sideband : 40(40 is enough to get accurate results in my case)
Noise type : Jitter(Typically, ADC needs only RMS jitter, not phase noise)
After PSS/PNOISE simulation, I caculated k-cycle jitter because the VCO is autonomous system and I need accumulated RMS jitter.
Following is what I did.
Results->Direct Plot->Main Form->select pnoise jitter(Analysis)->Jc(Function)->Number of cycles=1000->select RMS->
->Freq. Multiplier=1->Integration Limits:1kHz~20MHz
Here are two questions as I asked above.
I think the integration range of 1k~20MHz is enough, because total ADC's conversion time is 100us and 20MHz=10MHz(Fundamental X2)
Is it proper approach?
I believe the Freq Multiplier (which is really not clearly documented - it just says in various places that it defaults to 1, but gives no explanation, even in the documentation for the underlying functions drplRFJcc etc, as to what it actually means) is to allow you to say that you want the frequency used for the jitter calculation to be multiplied up from the frequency found in the PSS analysis. An example where that might be useful is when you have a divider and the PSS has found the divided frequency - but yet you are measuring the jitter elsewhere in the circuit (maybe on the divider input), and so you need to multiply the frequency of the PSS by the divide ratio of the divider to use the correct frequency in the calculations. However, I think you should log a service request to confirm this and request that it is properly documented.
If your PSS fundamental is 10MHz, and you are using the PMjitter mode, you should not sweep the pnoise beyond half the PSS fundamental (5MHz). This is because the PMjitter mode adds an ideal sampler to the output of the circuit and this is sampling at the PSS fundamental rate - sweeping beyond this will alias the noise and cause overcounting of the noise. Since the sampler is there, it will automatically fold any noise into the output band anyway, so it should be sufficient to have an upper limit of 5MHz. The lower limit of 1kHz is OK, but in practice if K is 1000 you are only including frequencies as low as 10MHz/1000 - i.e. 10kHz. The integration automatically takes this into account - so it's fine to leave it as 1kHz.
You might want to read the Jitter app note at <MMSIMinstDir>/tools/spectre/examples/SpectreRF_workshop/JitterAN.pdf
In reply to Andrew Beckett:
Your comment is really helpful to understand PSS sim.
Thank you for your reply, Andrew
I read the app note you suggested(for version MMSIM6.0, March 2006), and I'm little confused about k-cycle jitter.
From the note, section "Synchronous Jitter Versus Accumulating Jitter", autonomous circuits, e.g. VCO have only cycle-to-cycle jitter as the jitter performance as mentioned below
"For autonomous circuits where there are no ideal reference transitions, you are limited to using self-referred jitter metrics. This jitter is accumulating jitter. The next cycle transition is the result of the previous cycle output, so the jitter variance accumulates from cycle-to-cycle"
But, in the Figure 1-9 of the note, Cycle jitter is used as the jitter performance of VCO.
Could I use the K-cycle jitter as accumulating jitter of autonomous circuits?
Which is right?