Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I had to design my own transmission lines in layout and I have used HFSS to EM simulate the structure and then I use the result by employing NPORT in my schematic.
The problem is that I cannot run LVS since it does not produce netlist for a schematic that contains NPORT.
Any idea how I can run LVS while keeping my transmission line?
It depends on whether you want to be able to recognize the structure as part of the LVS, or whether it is just going to be seen as routing by LVS.
Either way, I would probably create a symbol for the structure, and then have two schematics. One schematic would connect all the ports of the symbol to corresponding ports of the nport - so it's a simple wrapper around the nport.
The second schematic would be for LVS - and this would either use cds_thru (from basic) to create effective shorts between the pins representing the opposite ends of each line, or it would use metal resistor components from your PDK. If use use the latter, you could mark the nets on the layout with whatever marker is used to identify a metal resistor (or place an instance of the metal resistor). This allows you (at least) to verify that there is something specific on the layout to distinguish it from a simple metal track - but whether it is worth doing this or not is debatable, since what you'd be verifying is nothing more than the presence of some marker layers...
There's probably other ways, but hopefully this is a start.
In reply to Andrew Beckett:
Thank you so much Andrew.
Finally I replaced the TL with PINs to do the LVS.