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I hope you all are doing fine. I need some guidance regarding post-layout simulation of black-box digital cells from Artisan Standard Cell Library using Ultrasim. We have the verilog, lef and tlf files in the PDK along with CDB symbol database that we converted to OA database. We have imported verilog view in the library and therefore we have the symbol, cmos-sch and the functional views.
For example, I have done the automated layout and P&R using Encounter for two inverters in series. I have imported the gate-level netlist and the gds file in Virtuoso and have been able to succesfully perform DRC and LVS (using the black-box cells parameter for the LVS). The pre-layout (post-synthesis) simulations have also been successful using the Hierarchy Editor, changing the Standard-Cell's view to functional and using Spectre-Verilog or Ultra-Sim from inside the ADE.
However, when we create the av_extracted view, since the inverters cells are black-box, they are not present in the extracted netlist. When we create a dspf file from RCX extraction, the cell instance is there. But we run into following issues:
1. What is the method of using a dspf file through hierarchy editor? When we specify it as a source file there, it is not able to see through the hierarchy and find the embedded inverter cell instances.
2. Are we supposed to simulated the dspf in UltraSim through command-line? From here, UltraSim looks for subckt definition of inverter cell, which we do not have. Since the DSPF already has all the interconnect parasitics, we believe connecting a functional instance in that netlist would also suffice. But how to include the Verilog cell definition while using UltraSim through command-line?
Thanks and best regards,
Hi arsalanYou can also specify the dspf file in ADE-L as follows:a. Set simulator as ultrasimb. Go to "Simulation->Options->Analog"c. Select "Post layout" tabd. Press the "Setting" button for "Parasitic RC stitching"Hope that this will help to solve your problem.Best regardsQuek
In reply to Quek:
Thanks for your reply. I specified the dpf file as per your advice and the simulation has completed successfully and a graph is also plotted but results are not correct! Actually ultrasim is not able to find the 'INVXL' subcircuit. (which is Artisan's standard cell). Here is the message:
Notic from UltraSim in 'INVXL'
Subcircuit 'INVXL' is empty.
Please tell me how ultrasim would be able to identify or locate functional/verilog description of INVXL, i.e. dpf file has had all the required extracted 'R' 'C' parasitics and INVXL at the end of dspf (or dpf) netlist as:
Xg2 g2#VDD g2#VSS g2#A g2#Y INVXL
In reply to BraveHeart:
Hi BraveHeartActually Ultrasim is a fastspice simulator, it does not interprete verilog codes. Our mixed signal simulator AMS Designer will be able to do that. You will need to add spice description of the standard cell netlist as one of the model files.Best regardsQuek
Thanks for the post. Actually I have not used AMS before. Before AMS people were doing mixed signal post-layout simulations using ultrasimVerilog, so i should be able to do that as well. I tried with ultrasimverilog and spectreverilog to carryout postlayout simulations but i am getting following errors.
The design doesnot have any interface nets connecting analog and digital components,......
I have sucessfully done mixed signal simulations before but this time i am performing postlayout simulations. In the Hierarchy Editor i have selected av_extracted view of inverter, which is analog view, the simulator fails to identify any digital part in the netlist, thats why it give the above error regarding interface nets.
My question specifically is; How should i use ultrasimVerilog to do postlayout simulations; In HE i need to select av_extracted view, (By the way i also used options -> Mixed signal options -> digital delays -> use existiung layout and provide the dpf file there) but then, there is no digital, hence no mixed-signal, therefore an error occurs while netlist is compile. How do i tell the simulator to take av_extracted view for detailed parasitics and use verilog/functional view of INVXL???
I would really appreciate your kind support since i am badly struck in this quagmire.