Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
If I place my Pcell by hand the cell works fine. Sizes are what I expect them to be.
Gen from source gives me small values that can't be laid out.
The symbol though has "90n M" which doesn't match other tech files I've worked with "90n"
I've tried two different ways of doing the CDF:
cdfCreateParam( cdfId ?name "w" ?prompt "width" ?defValue "0.2n" ?parseAsNumber "yes" ?type "string" ?units "lengthMetric" )
I've also tried the following default value:
?defValue sprintf(nil "%g" minMosWidth)
Neither gives me the desired result. Any thoughts?
Without seeing your pcell, who knows what the problem is. Most likely there is a difference between what the pcell is expecting and what the CDF value is - either in the type of the value it sees, or in the value. Maybe the pcell is expecting the value to be in microns?
Above you seem to be setting the default value in the first case to 0.2 nm (which is a bit small and rather ahead of state of the art technology).
In reply to Andrew Beckett:
Your right Andrew, I should have .2u not .2n.
That didn't solve all the problem with the size tho.
The Pcell code is:
; Define formal parameter name-value pairs. ( ( w 0.2 ) ( l 0.09 )....
width = w length = l
So I don't change the value in the Pcell. If I multiply w by 1*e-6 then virtuoso locks up when I load it. Kinda strange.
Any more thoughts?
In reply to MarkTown:
The type of the pcell parameters is float, but the type in the CDF is string - so you have a mismatch. They need to be consistent, and ideally the default values should be consistent. In this case you have the w in the pcell in microns, but the CDF in metres. Consistency is the key.
You could define the default values in the pcell as also being strings, and then use something cdfParseFloatString() in the pcell code to convert to a number, and do whatever scaling you need.
Thanks for the help. I got all the params to be consistent and then the sizing in the Pcell to work.
Well, turns out there is still an issue with the size of the Pcell.
If I places the nsoi Pcell thru layoutXL gen from source I get the correct size transitors.
If I instanciate the pcell from my layout cell I get very large transistors. This makes sence in the way I've changed the Pcell code to get it to work with the gen from source.
; Define formal parameter name-value pairs. ( ( w "0.2" ) ( l "0.09" )....
these lines work with gen from source.
These lines work when pcell is instanciated.
; width = cdfParseFloatString(w); length = cdfParseFloatString(l)
I currently don't have any call back called.
There is the CDF code:
;;; Parameters cdfCreateParam( cdfId ?name "w" ?prompt "width" ?defValue "0.2" ?parseAsNumber "yes" ?type "string" ?units "lengthMetric"; ?callback "nsoiCB('w)" ) cdfCreateParam( cdfId ?name "l" ?prompt "length" ?defValue "0.09" ?parseAsNumber "yes" ?type "string" ?units "lengthMetric"; ?callback "nsoiCB('l)" )
Anyone got any thoughts about where the conversion should take place from schematic to layout?
My guess is that your schematic has the components instantiated with values such as "0.2u" - and so with the scaling lines in the pcell, it correctly transforms it into layout units (microns).
When you're instantiating in the layout directly, and picking the value as the default (0.2), then that scaling would result in a transistor width of 20cm - which is a tad large.
So it's a units mismatch problem - you need to decide what values you want the user to enter, and then be consistent about it. Maybe your pcell default and CDF default should be "0.2u" and then you will need the scaling in the pcell to convert into microns since the layout will be drawn in microns.
A bit of a guess because obviously I can't see everything...
Yes, Andrew, I'm aware that its a units issue. I've tried quite a few different units trying to get them to match. I get the code working one way and then it breaks another way.
For something as easy to mess up as this, it would be nice if CD not only had an example like the 90nm sample code but also an explanation of why each cb, cdf, il and symbol has to be what it is and why. Where the conversion should be etc. I've thought I had ever line matched up with the CDS examples and yet it still didn't work.
So now its just going to ahve to be skill code that is placed. Its easy to make that work. No gen from source in this version.
thanks for you help
There is ABSOLUTELY NO REASON why you should not be able to make it work for both scenarios. Once you've decided whether the user will be setting the dimensions in metres or microns on the component, you can make it consistent everywhere.It would be very odd if you specified the dimensions differently when placing an instance on the schematic from placing an instance on the layout.
This is not complicated - so I'm slightly mystified as to why it is seen as being complicated.
Yup, I know there isn't a reason. But I've not been able to do it in 2 weeks of trying.
I've never been this flustrated trying to program in CDS.
Would you like to create a Service Request to get support directly from a Cadence engineer? This would likely give you better support than the online forum, especially if you have reached a point of frustration...
Didn't I just explain how to do this though? I don't really understand what the remaining issue is.
Maybe you should log a service request so that a Cadence AE can see the actual data you're using rather than just a few snippets of it?
I had a service requite on this going as well .... after a couple of rounds they said theyweren't suppose to program for me. I just wanted them to explain why things were matching etc. tech said maybe I should look into paying for some help. But noone hear is willing to pay it seems.
I kept pluggin along. Seem to get things working, then somethings breaks. Been around block 2 or 3 times by now.
Maybe I'll create an other service request and ask for someone who know this stuff. The guy I had didn't seem to reall know the details about this issue.
If you let us know the service request number, Lawrence or I can take a quick look.