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Hello,a question from a Cadence beginner:
It is difficult to debug this issue without seeing the specific testcase but the following pointers may help to resolve the problem You mention that the “program highlights the DIFF/Poly crossing (channel) to indicate an error” - I can’t say for sure why you are seeing an error here but by using Markers-Explain you can query the problem and this may help to explain what the issue is. Check against source could also be run to find differences between the schematic and layout. Xprobe can be used too check the connectivity. I don’t think that flattening the hierarchy is the solution here. It would be better to create the layout instances to correspond directly to the schematic instances because in VXL we are not able to create correspondance with *shapes*, only with nets and instances. If the instance names match between the schematic and layout the correspondence will be created automatically, if not then this can be achieved by using Create Device Correspondence and Updated Device Correspondence commands. Full details of these commands are available in Chapter 12 of the Virtuoso XL Layout Editor User Guide. It can also be achieved by adding an lxUseCell property on the instances in the schematic; again this is documented in the user guide
Hi Alexc,thanks for your response!> because in VXL we are not able to create correspondance with *shapes*, only with nets> and instancesIn my case this feature would be very helpfull. I have an existing layout without instances (only *shapes*) that must be redrawn with different scale of the transistors. As the layout is quite complicated and optimized by hand, I can't simply replace the existing transistors with "new" instances as it is simply not possible to generate exactly the look and feel I need in my specific case. By now my approach is scaling the whole layout, adjust some parts not to be scaled (e.g. contacts) and that's it. Everything works fine except VXL not recognizing the transistor instances. Therefore I was searching for a feature like "take shape 1,2 and 3" and tell VXL "this is now instance XYZ". Nevertheless all this stuff isn't as important any more as it was one week ago. I at least convinced the LVS Checker to automatically detect my handmade transistors and find the corresponding ones in schematic. As I am a really stupid boy, I forgot to paint an additional layer to signal thicker oxide that is part of the transistors/instances in schematic and simply does not exist in the old layout with thin oxide I used as pattern. The LVS Checker didn't find the schematic instances in layout because of the layer difference between schematic and layout. Now that I added the thick oxide layer LVS works fine and that was all I wanted for now.Thanks again for your help!