Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Does anyone know where i can get a detailed report on unsuccessful/incomplete routes in VCAR i.e why did it not complete? I can see that some of the unrouted nets would be easily done by hand. Does VCAR get its connectivity from the layout/schematic/somewhere else?
Welcome to the community! I'm the community manager so don't have the expertise to answer you question -- someone else will be along I'm sure to do that -- but wanted to encourage you to go into your profile and choose a screen name. You can also upload an avatar if you wish. :)
Cadence community manager
I apoligize for the much delayed response and hope that you were able to get your questioned answered through another method such as CDN Customer Support or your local AE.
For the benefit of the forum and other users I'll provide a response.
In response to your first question, "Does anyone know where i can get a detailed report on unsuccessful/incomplete routes in VCAR i.e why did it not complete?" Yes, their are several reports that you can generate to get information in VCAR. For your specific request you can try the following report:
Other reports that you can use:
Report > Nethttp://sourcelink.cadence.com/docs/files/Release_Info/Docs/iccraft/iccraft6.1.3/report/report_net.htmhttp://sourcelink.cadence.com/docs/files/Release_Info/Docs/iccraft/iccraft6.1.3/info/net_report_info.htmReport Networkhttp://sourcelink.cadence.com/docs/files/Release_Info/Docs/iccraft/iccraft6.1.3/report/report_network.htm
Report > Net
In response to your observation related to your first question, "I can see that some of the unrouted nets would be easily done by hand." there are several ways to analyse and investigate why a connection is not made. First, if the connection failed automatically try to route it interactively. If it succeeds it may indicate an autorouter setup problem or bug. If it cannot route interactively or automatically it may indicate that the connection point is blocked or a rule is set prohibiting the connection. Make sure to also use the 'check' and 'report' features to show conflicts which may indicate the cause of the incomplete net.
In response to your second question, "Does VCAR get its connectivity from the layout / schematic / somewhere else?" it really depends on your design flow and tools. VCAR can get it's connectivity from a variety of sources including the connectivity associated with the design in VXL from the layout and schematic in CDB and OA formats, DEF, translation from proprietary applications that generate the correctly formatted netlist section in the design file.
I suggest referencing the Virtuoso Chip Assembly Router Guide if using a Virtuoso flow.
For IC5141 CDB reference: http://sourcelink.cadence.com/docs/files/Release_Info/Docs/iccausr/iccausr5.2.51/iccausrTOC.html For IC61x OA reference: http://sourcelink.cadence.com/docs/files/Release_Info/Docs/iccausr/iccausr6.1.3/iccausrTOC.html
For IC5141 CDB reference: http://sourcelink.cadence.com/docs/files/Release_Info/Docs/iccausr/iccausr5.2.51/iccausrTOC.html
For IC61x OA reference: http://sourcelink.cadence.com/docs/files/Release_Info/Docs/iccausr/iccausr6.1.3/iccausrTOC.html
I hope this answers your questions. If not, feel free to add to the post. I also recommend contacting Customer Support and your local AE to assist you in your use of VCAR.
Craig Thompson Sr. Technical Leader Technical Field Operations, North America-Central Region 866.225.3138