Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
well apart from doing what you've said (using A<1:5>) and modifying the pitch so that when you remove the unwanted pins everything is correct, the only other suggestion that I can make is to use the leCreatePin() SKILL function with a wrapper around it to use it multiple times, once per pin. You could use an enter function to gather points from the user (e.g. enterBox) and have a command form so that you can control the bus expansion part. This might be a lot of work if you are not going to use it all the time, so I'd suggest using the first approach.
In reply to skillUser:
Thanks a lot. I don't know much about SKILL, so probably I will use the first approach. Do you mean for example, I first creat a bus A<1:5>, delete A<2> and A<4> manually, then I get A<1:5:2> with desired pitch?
In reply to Finn:
Hi,Yes, that was the idea, basically to create the superfluous pins so that the automatic pin creation could be used, and then to delete the unwanted pins, either manually or through SKILL.The latter would be relatively easy to do, for example, theterminal objects can be found one at a time by using the SKILL function dbFindTermByName(), or something like this:
cv = geGetEditCellView()
a_terms = setof(term cv~>terms rexMatchp("A<" term~>name))
=> (db:215089524 db:215089592 db:215090640 db:215090688 db:215062840)
a_terms~>name=> ("A<5>" "A<4>" "A<3>" "A<2>" "A<1>")
even_a_terms = setof(term cv~>terms rexMatchp("A<" term~>name) && evenp(atoi(cadr(parseString(term~>name "<>"))))
=> (db:215089592 db:215090688)
There may be more things to remove...