Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
for acedemic purposes I would like to use a custom made level 1 MOS transistor model in my Spectre simulations (I am using Cadence 6.1.3). In my opinion using a verilog-a transistor model is a good solution for this, because I can adjust the transistor behaviour on equation level or is there a better way?
In order to do so I built a very simple test schenmatic and used the given "mos_level1" verilog cellview from the "ahdlLib" library inside the schematic.See the following picture:
Then I start ADE L and set up an DC analysis (with Vds as sweep variable) and a parametric analysis to sweep Vgs. But when I start the parametric analysis I get the following error message:
Begin Incremental Netlisting Feb 5 16:17:04 2010ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch schematic', for the instance 'I0' in cell 'HighDimensionalVCO1'. Either add one of these views to the library 'ahdlLib', cell 'mos_level1' or modify the view list to contain an existing view. End netlisting Feb 5 16:17:04 2010ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be corruptor may not be produced at all.To generate correct netlist, fix the errors and re-netlist.Simulation unsuccessful during parametric sweepStopping parametric simulation
I have never worked with verilog models in Spectre before. Maybe this is not the right way to use a Verilog model in the Spectre simulator. I am glad for any help...
Thanks in advanceJan
In ADE, in Setup->Environment, you need to make sure that "veriloga" is in the Switch View List. In fact it's odd that it isn't because normally it would be there by default.