for acedemic purposes I would like to use a custom made level 1 MOS transistor model in my Spectre simulations (I am using Cadence 6.1.3). In my opinion using a verilog-a transistor model is a good solution for this, because I can adjust the transistor behaviour on equation level or is there a better way?
In order to do so I built a very simple test schenmatic and used the given "mos_level1" verilog cellview from the "ahdlLib" library inside the schematic.See the following picture:
Then I start ADE L and set up an DC analysis (with Vds as sweep variable) and a parametric analysis to sweep Vgs. But when I start the parametric analysis I get the following error message:
Begin Incremental Netlisting Feb 5 16:17:04 2010ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch schematic', for the instance 'I0' in cell 'HighDimensionalVCO1'. Either add one of these views to the library 'ahdlLib', cell 'mos_level1' or modify the view list to contain an existing view. End netlisting Feb 5 16:17:04 2010ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be corruptor may not be produced at all.To generate correct netlist, fix the errors and re-netlist.Simulation unsuccessful during parametric sweepStopping parametric simulation
I have never worked with verilog models in Spectre before. Maybe this is not the right way to use a Verilog model in the Spectre simulator. I am glad for any help...
Thanks in advanceJan
In ADE, in Setup->Environment, you need to make sure that "veriloga" is in the Switch View List. In fact it's odd that it isn't because normally it would be there by default.