Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am using Version 126.96.36.19907.isr10. And the technology is UMC180nm.
I am trying to do some montecarlo simulations using both "n_lv_33_mm" and "n_33_mm" transistors.
In fact, the simulations are performed well when I use only "n_33_mm" transistors. However, when I include "n_lv_33_mm" transistors in the schematics, it shows the following error:
Error found by spectre during circuit read-in.
ERROR (SFE-74) : Error found in protected block by Virtuoso (R) Spectre during circuit read-in.
Now, I have added the all three montecarlo corners and I think the model libraries corresponding to the low vt transistors are included. Not sure if i can post the full names of the model libraries here though.
If I don't use one of the MC corners, it will show the error:
ERROR (SFE-23) : "input.scs" M0 is an instance of an undefined model n_lv_33_mm.
Thanks in advance,
Your best bet would be to contact whoever supplied the models/PDK (presumably UMC). This requires detailed knowledge of how that PDK is set up to be able to answer it.
In reply to Andrew Beckett:
when I meet the question like this ,how can i get the error info according to the error code(which like SFE-74)?
In reply to GiiFlying:
SFE-74 is the error code for "Error found in protected block by Virtuoso (R) Spectre during circuit read-in.". It is not an error code corresponding to the real error underneath.
The reason why the real error is suppressed is that people could do things which would force an error within an encrypted block to reveal information about the protected block contents. For example, you could invoke a subckt with the wrong number of terminals, or with incorrect parameters, or attempt to reference a node or component within an encrypted subckt knowing full well that it will fail - this type of thing could unwittingly reveal information that the person who encrypted the netlist wanted to protect.
You probably need to contact the original provider of the encrypted file for assistance.
I see.Thanks a lot.