Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I am using IC6.1.5-64b.500.12
When I call Instances from schematics to layout using "generate>selected from source", it places the instances multiple times. Also all the instances are placed at origin
Any idea why this is happening ? and how to solve this issue ?
I'd normally expect this if you have a parameter called m to act as a multiplier. If you don't want to have "m" treated as an m-factor, you can prevent that from the XL Options form.
In reply to Andrew Beckett:
Thanks andrew for quick reply. But unfortunately that did not help.
I have attached a snapshot for more clarifications.
thanks & reagards,
In reply to Roopak25:
Unfortunately I don't think I can help much seeing a picture at that level of detail - this would be best handled by you contacting customer support, and then somebody can take a look at your data (either by you sending it, or via remote web-sharing session).
Did you fix your multiple instances issue? I am facing the same issue and I don't know how to solve it.
In my particular case, I have a single inductor in the schematic and when I transition to layout XL, I get 5 instances of that inductor.
For those who want to take a look, please click on the picture to see the layout window as well.
In reply to gabriel rf:
This is probably because your inductor has a parameter called "s". Go to Options->Layout XL, and on the Parameters tab, in the section labelled "Schematic Parameter Names", change the cyclic field to "Series-connected factor". It's probably showing "s S" as the value. Change this to something that doesn't include "s" (e.g. "sdummy").
What it is probably doing is misinterpreting the s=5u as 5 series connected instances...
Thank you for your answer. I checked the settings you mention, even changed to sdummy, but that did not remove the extra instances. However, at some point they disappeared, but I can't tell for sure what I have done.
In the mean time, I took a different approach. I have manually instantiated the inductor, then I ran LVS to confirm the sync with the schematic. It worked and I've been able to run and plot simulations for the ideal schematic and the extracted circuit that includes the parasitics. The differences are visible.