Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
When I am using a config file set to a schematic view, I can see the underlying cells and their respective views which I can change individually to lets say, calibre or spectre. When I then switch the config top cell view to adexl, I can view the top level cell but not view or change hierarchical cell views. Is there a way to change then underlying cell views when using adexl and a config file. Any suggestions would be appreciated and would greatly improve my efficiency. Thanks.
I suspect you've misunderstood something here. Config views are intended as a way of describing the rules by which a design hierarchy is expanded, and are typically consumed by tools that need to expand the hierarchy (such as the netlisters used in ADE L/XL/GXL). So it's reasonable that ADE XL allows you to describe one or more tests where the design is specified as a config - and that will tell it how to expand the hierarchy (which views you want to simulate) for that test.
It makes no sense for a config view to reference an ADE XL view. The ADE XL view is nothing to do with the design hierarchy - so I can't see why you'd ever want to do this. What would you expect to do with the resulting config? If you consumed that resulting config in (say) ADE XL, what would you expect it to do when it encountered an ADE XL view in the config? Especially as the ADE XL view could be describing multiple tests, each with different designs.
So I think you're probably thinking about this back to front. You use the config to describe the hierarchy expansion, and then reference that config from the ADE XL view, not the other way around.
In reply to Andrew Beckett: