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I am performing a complete digital implementation flow to a given circuit. I started with behavioral vhdl, used Cadence Buildgates with osu018 std cell library and obtained structural verilog format. Next, I used Cadence SOC Encounter for place-and-route, exported .gds output format and imported into virtuoso to obtain a final layout and extracted a spice netlist out of it. My experimentation is supposed to be on this final netlist.
My problem is I need to insert a transistor level sensor circuit into my original circuit. I am really not sure in which phase to insert it. I am not able to insert it during structural synthesis as my transistor level circuit cannot be represented to standard gates. I am not even able to insert it in final spice netlist as it is not really structural.
Please let me know if you have any ideas.
Hi ShinyPerhaps you need to do it as follows:a. Design the sensor schematic in Virtuosob. Create the sensor layout in Virtuosoc. Generate abstract view for the layout using abstract generatord. Export LEF file from the abstract viewe. Manually edit your structural verilog netlist to include a blackbox representation of the sensorf. Do place & route in Encounter using the additional LEF file and modified verilog netlistBest regardsQuek