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Hello all.I'm a trained physicist trying to get to grips with Cadence Virtuoso. I'm now designing a custom IC and have had a few issues. I'm using AMS 0.35 um technology kit (not sure if this info is particularly important but thought I would include it anyway).When doing the DRC I am met with the following:AMTS1 Maximum MTOP spacing when the width of one or both MTOP shapes is less than 10um.I have looked on these forums and elsewhere but cant seem to find what out a) what this error means (I'm guessing it has something to do with the top metal layer) b) how to correct the error.Any assistance is much appreciated.Many thanks,James
You should look up the rule in your Design Rule document for the process you're using. Almost certainly they've given the rule names in the DRC deck similar names to what they are in the documentation.However, it suggests that shapes on the top metal need to be spaced no more than a certain amount if either shape involved is less than 10um wide. Some kind of density rule. But without seeing the design rule document, I couldn't say. If you're really unsure, ask the provider of the technology...Regards,Andrew.