Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
hello all,This seems a silly error however I've spent the last hour trying a variety of things to solve it but ultimately have been unsuccessful :(When I run DRC of my layout I get the errors, "net_nwell net_welltap : Has Multiple Stamped Connections""net_nwell net_welltap : Causes Multiple Stamped Connections"When I zoom to markers Virtuoso flags a simple contact I have to an n well. I used the Create > Contact option for this simple contact (i.e. not hand drawn). Admitteldy the contact area is very big compared to typical CMOS contacts (I have 20 columns x 80 rows contact openings) but I do not see how this should matter.Does anyone know how to solve this frustrating issue?Many thanks,James
James,Generally speaking this kind of error means that you have more than one well contact, with the metal connected to different nets. This means you've got a "soft connect" through the well (not quite a short, because the well is resistive). It may be that you're making a connection via the well, which is almost certainly not what you want!So check what other well contacts you have in the same well, and what they're connected to. If the connections are made in metal as well as nwell, the error will (most likely) go away.Regards,Andrew.
Hi Andrew, thanks for your comments.Within my nwell I have a vertical pnp bipolar transistor. The base region is connected to ground. I think this may be causing the problem since I have the (n-type) base of the vertical pnp transistor connected to ground while the rest of the nwell is connected to a different potential (N.B. the nwell will not be connected to vdd as is standard. My n well will be connected to a +ve potential but for the purpose of subsequent electrochemical etching). So I can see how Virtuoso/DIVA (whoever) can see my nwell is connected to 2 different potentials HOWEVER in actual operation of my circuit the nwell will not be connected to any potential. The vertical pnp bipolar transistor connections contained within my nwell will have the base and collector diode connected to ground. So I have two options: 1. Somehow get DIVA to acknowledge that there are two connections to my nwell but in practice there will only be one (not sure how to do that) or2. Draw a second n well within my original n well and then within this second n well define my vertical pnp transistor. This way my two n-wells will have different potentials. However I'm not sure about parasitic transistors/pn junctions associated with this configuration.