How to create dependent voltage source?

Simplest way would be to create a subckt like the following in an external .scs file:

//
subckt forumDep (plus minus ap am bp bm)
V1 (plus minus) bsource v=v(bp,bm)<1?v(ap,am):v(bp,bm)
ends forumDep

Then you could create a symbol for this with 6 pins, and in the CDF (in the spectre simulation information) specify the component name as "forumDep" and the termOrder as the list of the symbol terminals in the order that corresponds to the order in the subckt (here I gave each input a positive and negative pin, but obviously you could change that).

Then specify the file with this definition in using the Setup->Model Libraries in ADE. 

Watch out though - the above source is not continuous, so behaviour at the transitions may be a little unexpected.

You can also write something similar using Verilog-A but I'll leave that as an exercise for you.

Regards,

Andrew.

Thanks a lot.

I have just tried it but there is one error relating to netlist as follows:

ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the
instance 'I3' in cell 'DepSrc_tb'. Either add one of these views to the library 'Huan',
cell 'forumDep' or modify the view list to contain an existing view.

Here is what I did:

1. Create a file titled external.scs with the content as below:

subckt forumDep (plus minus ap am bp bm)
V1 (plus minus) bsource v=v(bp,bm)<1?v(ap,am):v(bp,bm)
ends forumDep

2. From schematic editor, create a symbol as below:

3. Edit CDF

4. Create a test circuit

5. Refer to the file external.scs from ADE --> Model Libaraies

6.  Run from ADE and I got the error above. 

Sorry - I forgot to tell you to copy the symbol you created to a view called "spectre" (same lib/cell). This then acts as the "stopping view" for the netlister - it's a marker so that the netlister knows when it switches into it, that it should stop expanding the hierarchy.

Once you've done that, it should solve the problem.

Regards,

Andrew.

Thank you. 

It works now. However, at transitional time the result is not correct. 

You said that the above source is not continuous, so behaviour at the transitions may be a little unexpected. Could you explain why?

I read the code above and didn't see why it is not continuous.

I disagree that the behaviour is not correct at the transition points - I encoded exactly what  you asked for, and the actual points in the waveform are correct (you can't read anything into the lines between the points).

The problem is that the output follows the voltage on b all the time b>1V. As soon as b is less than 1V, the output suddenly changes to be whatever a is - so the output value has a sudden change at the transition (b crossing 1V) from b to a (or vice versa). How smooth that transition is in the output waveform depends on the number of time points at the transition region. Secondly, there's nothing in the source to guarantee a time point at exactly the transition point (you could do this with @cross in Verilog-A, but even then you'd have a discontinuity in the output, unless you put in some kind of smoothing function).

Maybe you'd be better off using a relay in spectre (the "switch" component in analogLib - you'd probably need a couple of these)? 

Andrew.

Thanks. I don't know why but I tried the code above but the result is wrong in the transition points.I run transient analysis and there is a time period about 35ns where b< 1 but V1 (plus minus) is not equal to v(ap,am) but it is a linear.

subckt forumDep (plus minus ap am bp bm)
V1 (plus minus) bsource v=v(bp,bm)<1?v(ap,am):v(bp,bm)
ends forumDep

I am not at school right now so I can't plot the signal. However, here is the idea:

I did try switch but I don't find a way to do that.

However, this is the first time I did something like this. It is interesting too. I think I will study more about this when I have more time.

It seems that with verilogA we can create almost anything we need.

I'm guessing that the "linear" response you're seeing is because there's a timepoint at 35ns before the transition, and the next time point is at (or near the transition). If you were to set maxstep on the tran analysis to 1n (say) then you'd get something much sharper (note, this is NOT the right thing to do as it will harm the performance of the simulator). Essentially you're expecting there to be a instantaneous transition of the output from 0.6V to 1V at the point where b goes above 1V. Circuit simulators don't do "instantaneous" because there's no such thing as instantaneous in real life - that's a discontinuity. 

Because this is uncontrolled, the simulator is not attempting to follow this sharp transition (because it doesn't know it's going to happen until b>1V - it's seen no need to insert additional time steps before the transition). As I said, the points are correct - this is what the simulator actually solves. The lines are just a visual aid drawn by the waveform tool, and adding discontinuities is a good way of getting confusing results.

When  you use a bsource, it's effectively building a very simple Verilog-A model behind the scenes, but without the full power of Verilog-A. With Verilog-A, you could write code to manage the smooth transition between these discontinuous values, and effectively control the time constant of that transition - but equally you could write Verilog-A code that completely fails to do this in which case you'd create this discontinuity. Discontinuities can be very bad because the simulator may try to follow them and it could cause the simulator to take very short time steps in order to resolve the discontinuity - harming performance. Similarly the idea of setting maxstep was just to observe the effect - if you do that, it would cause the simulator to take small time steps all the time, which is also bad news for performance.

In general, any modelling you do in Circuit Simulators should aim to be realistic, not idealistic.

Regards,

Andrew.

Hi again,

You are right. I have just tested it with maxstep 5ns and the linear region is now narrowed to only 1ns. 

As you mentioned above and in other posts, setting maxstep like that will affect the performance of the circuit.

However, in some circuit which includes oscillator, it is necessary to set the maxstep parameter. Is there an optimal value for this in a certain circuit?

In most situations you should not need to set maxstep - so the optimal value is generally to not set it!

One of the few cases I do set it is when I have an oscillator which is slow to start. With an oscillator, the DC operating point may find a metastable state and since there is no external stimulus, a transient may remain at that metastable state with very long time steps hitting the default maxstep (either 50th or 100th of the simulation interval, depending on errpreset) which may be insufficient to allow the oscillation to build. So with oscillators you may need to give it some kind of kick (to force it away from the metastable state) and force more time steps (I typically would pick a 20th or 50th of the expected oscillator frequency) to allow the oscillation to grow more rapidly.

Certainly in this case though it would just be a crutch for poor modelling - if the modelling of your dependent voltage source properly handled the discontinuity, there would be no need to set maxstep.

Regards,

Andrew