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explicit wire decalration by virtuoso verilog netlister

stanzani

Hi all. 

When I generate a verilog netlist  out of virtuoso ncverilog netlister I see that  implicit net s(those internal to modules) are not esplicitly declared. Is there any way to force the netlister to explicitly  declare implicit wires. 

When implicit nets are multidimensional the netlister declare them. I think there's a way to force this behavior also for scalar wires.

 

Please help, 

thanks in advance.

  • Off the top of my head, I don't know if this can be done - I can check. However, first I'd like to understand why you'd want this? It's not required in the Verilog language (whereas it is for non-scalar nets).

    Regards,

    Andrew.

  • Hi Andrew,
    I have the same need.
    The problem is that I perform a post elaboration of the netlist changing all the input, output, inout ports and declared wires type to a user defined nettype(this is done in a system verilog context).
    The problem arises since the implicit nets are not declared so their type cannot be changed a simple substitution. Irun assign them the wire default type. So during elaboration a wire type is passed to a user defined nettype(in my case a real net).
    If the implicit nets are declared their type can be easily corrected to the other ports type.

    Best regards,
    Jack

  • Jack,

    The simplest solution (since you want a system verilog netlist) is to use the system verilog netlister! This does indeed declare wires for the scalar nets.

    Use (from the schematic) Launch->Plugins->Simulation->System Verilog

    Regards,

    Andrew.

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