Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I have a mixed schematic, mostly analog but with some embedded digital controllers. The digital parts were made in SystemVerilog and imported into the correct views in virtuoso together with the schematics. Then using RC and Encounter the schematics and layout views were generated and also imported into the database. The problem is some inconsistencies came up.
RC added pins for scan chain and Encounter had to buffer the clock trees and created the respective pins as well (clk__L1..., etc). These do not show up in the top level of the digital schematics, only between the internal blocks. Being these new pins do not exist in the RTL, anytime I open the SystemVerilog views I get error messages back from the tool stating the pins are not consistent with the symbol. If I just send it all to UltraSim or VerilogAMS with the netlist views it works fine, but when I try to use the SystemVerilog views with the schematics to run VerilogAMS the netlister quits with an error. The netlister will not run if the views do not match even though the SystemVerilog files do not need these extra pins.
I guess the simplest solution would be to change the RTL by adding these missing pins as dummy pins. A bit anoying as it would start cluttering the design and also would require some manual work after every change to remove the old added pins, add the new ones (as the names change in every run) and recheck all schematics and symbols.Remove the added pins does not sound like a solution either as they are in the layout and therefore LVS is going to expect to find them.
Being these are not new concepts I would think Cadence already has something in place to handle these issues of mixed environments. Anyone have any ideas?
which IC and EDI version do you use ? Since you're talking about layout views I assume you work on an Open Access Database.
Is you're PDK Mixed Signal enabled - means do you have your technology LEF available as an OA library referencing the Base PDK?
In reply to Andreas Lenz:
The IC is 6.1.5-64b.500.
The RTL Compiler is RC10.1.301 - v10.10-s313_1
TheEDI is version 10.10
As for the PDK, I am not sure what you mean. We received the PDK from the foundry with LEF, Synopsys files, netlists in CDL and Verilog, etc. As for the database we had to convert the LEF files and library netlists into OA so we could do full-custom analog+digital design. Then all our analog work has been done in OA in schematics and simulated using UltraSim. It is just when digital and analog meet that problems come up.
From Encounter, I exported the DEF and netlist files. Then imported both into virtuoso using verilogin and defin. When I did that the SystemVerilog views no longer matched the pins of the newly created schematic, symbol and layout views. Then, when using the regular gui invocation for VerilogAMS, I specify to use schematic views and it works great. If I specify that I want the digital subblocks to be using the SystemVerilog views it all dies due to the missing internal pins. And if I open the SystemVerilog RTL and save I get also a message back as the extra clock buffering pins are not in the RTL.
In reply to glennramalho:
I guess there is no automatic way. Cadence support suggested some parameters that killed some functionality and I was hoping for something that would not require changing the view one way that would not require manual effort. Experimenting we came out with a solution that I`ll share here.
* Tell the netlister to use the systemVerilog view for the digital controller top.
* Inside the ADE netlist options use the Stop View list and add systemVerilog to whatever else is needed for the analog schematics. Then the digital controller will show up as a black box. This eliminates all the internal pin checking. As I said the top level pins match the schematic, it is jsut the internal blocks theat don`t.
* Create a directory and inside it create a series of symbolic links. Each one should have as a name a SystemVerilog module. So controller_top.sv would point to .../library/controller_top/systemVerilog/verilog.sv, and controller_core.sv would point to ....../controler_core/systemVerilog/verilog.sv, and so on. (there are other ways to do this as well, via the -f option of irun, or via a file with several include statements)
* In the simulation options set the libext field to .v,.sv so that both SystemVerilog and Verilog are searched. In the -y field put in the symlinks directory. And also include with the -v or -y fields whatever models that the RTL views might need.
* Then tell the netlister to run and then start the VerilogAMS simulation.
Then you would need a netlister configuration for each type of simulation. One for UltraSim using schematics or perhaps VerilogAMS using schematic views. One for VerilogAMS with SystemVerilog, as described above.
I guess there is still a minor issue that any time I make a change to a systemVerilog view I get an error back when I save it. I probably would have trouble running a pure digital simulation from within virtuoso, but I usually do that from the command line anyways, so no harm there.