New Application Note: Phase-Locked Loop Design Using AWR Design Environment

AWR Design Environment is well suited for the design and analysis of a phase-locked loops (PLL) in both the frequency domain and then time domain. An application note with accompanying project files explains the process of designing a PLL. This application note is directed at the designer using commercial off the shelf components in the PLL. This higher level system design approach is achieved using behavioral models for all the components in the PLL.

Topic in the application note include:
* Development of behavioral models using data sheet specifications
* Open and closed loop analysis for loop stability
* Design of the discrete component loop filter
* System phase noise analysis
* Lock time analysis
* Yield analysis using statistical variation of device parameters
* Multi-loop PLL architecture

This application note can be found using this link: support.cadence.com/.../ArticleAttachmentPortal