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deepprobe with AMS

swdesigner

 Is there any way to get the solution 11017972 - accessing a lower level net from the top-level - to work with AMS?

  • Along the same lines, is it possible to create a component, somewhat similar to deepprobe, that can be used to create a voltage equal to a parameter of another component? Here's the motivation :

     

    I want to trim an oscillator in my simulation - in a DC simulation. The oscillator freq is based on an RC time constant. Getting an R in an operating point sim is easy. Getting the C is not possible - you have to run a transient, which I'd like to avoid. If there were a component I could use - say param2volt that creates a voltage source with voltage equal to the C of the cap of interest, my problem is solved.

     

    Any ideas?

     

    Thanks!

  •  Hi Guys,

     Did anyone try the deep probe (with or without the additional SKILL) with an OSS netlister?

     

    I did manage to get it to work with Cell-view, but I recently changed over to OSS to support up-to-date features.

     

    Whilst the simulation runs with the deepprobe, I get a warning during a transient run preamble, that the net

    Testtop\.IDUT\.ITOP\.IADC\.fastreset doesn't exist.  

    The net to probe in my deep probe symbol refers to that net, but without the '\' characters.  Why does it place those chars?

      

     

  • This works fine with the new "UNL" OSS implementation that is coming (it's currently under early adopter with a few customers), but there are no plans to fix it in the current OSS implementation (for reference, CCR 1089627). Unfortunately the translation code which translates spectre syntax to VerilogAMS incorrectly escapes the hierarchy delimiters.

    Regards,

    Andrew.

  •  That's a shame.....

    ok...I'll continue to use 'force' 'release' statements to 'logic' discipline nets for now.

     Cheers

  • I am trying to use deep probe in the ams environment but it does not seem to be working the way it does in the non ams environment. basically, I want to unbound a resistor deep inside the chip top hierarchy and add a RC filter between the terminals of the unbounded resistor using 2 deep probe elements at the top level of my TB. Is the format of naming the nets inside the deep probe different in the ams environment ? Please let me know.

    Thanks,
    Uzzy

  • Uzzy,

    I should be able to definitively answer this given that I created deepprobe in the first place, but I'm not able to do an experiment right now. If my memory is correct, you may need to use topCellName.I1.I2.net3 rather than I1.I2.net3.

    Regards,

    Andrew.

  • Hi Andrew,

    Thanks for the reply. I tried your method but it does not seem to work. The node inside the hierarchy is moving but the deep probed node at the top level trying to access the same node inside the hierarchy is not moving. So, when I used topCellName.I1.I2.vsense_lpf_adc_int inside the deepprobe, it netlisted as
    iprobe IPRB0 (\topCellName.I1.I2.vsense_lpf_adc_int , top_vsense_lpf_adc_int);

    Do you see what could be the problem ? Please let me know.

    Regards,
    Uzzy

  • Uzzy,

    I should have asked which IC subversion you're using (Help->About in the CIW) and which AMS netlister (under Simulation->Netlist and Run Options in ADE). From what you've shown I suspect you're using the OSS netlister, as this is the same problem as something I filed a while back (CCR 1089627) which was fixed by the UNL (Unified Netlister) which is available from IC616 ISR4 or 6 (I forget which). It's on the Netlist and Run Options form.

    The bug wasn't (and won't be) fixed in OSS as if you are using a new enough version it doesn't make sense to use anything other than UNL.

    Regards,

    Andrew.

  • Hi Andrew,

    This is what I am using:
    version IC6.1.7-64b.500.6
    NETLIST AND RUN MODE: AMS Unified Netlister with irun

    Regards,
    Uzzy

  • Hi Uzzy,

    I've checked. You don't need to (and shouldn't) put the top cell name in (that might have been needed with cell-based - I can't remember). Anyway, if I put the top cell name as part of the hierarchical path, the name gets escaped by the UNL netlist assembly process. If I just use I1.I2.vsense_lpf_adc_int then it works fine (in my example I'm using I1.I0.b). If the hierarchical path doesn't exist however, it seems to get escaped - so it's important that you get the hierarchical path correct. 

    If this isn't working for some reason (I don't see why - I'm using the example "testit" circuit that's in the tarball associated with the deepprobe article on support.cadence.com), please contact customer support - it must be something to do with the data you're using (maybe)?

    Regards,

    Andrew.

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