Stats

  • Locked Locked
  • Replies 11
  • Subscribers 126
  • Views 6758
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

QRC Parasitic Extraction Issue (netlist has source/drain flipped on many instances)

jimstuy

Hi,

   I am working on a analog design in Cadence IC6.1.4.500.5, and I have completed the layout of the chip with DRC, LVS, floating gate check that is clean (I amworking with IBM's CMRF7SF process).After I ran Assura QRC to generate av_extracted, and av_analog_extracted views I go back into my testbenches to run toplevel sims with these new views, and I am running into problems.

   I am comparing the netlist with extracted views, and I noticed that on many of the NMOS and PMOS devices, the source and drain is flipped from what I intended them to be in my design. For example, I expect N1 to have a netlist of N1(D G S B) according to my schematics, and instead of that, the parasitic netlist of the instance N1 has a netlist of N1(S G D B). Wondering why that's the case. I passed LVS, and this only shows up in av_extracted and analog_av_extracted views... Thanks for any tip/advice from you!

  • Hi jimstuy

    I think the addition of "\1\:" is for the subnets formed by the parasitic resistors between the terminals of R0 and the mos gate terminal. If you check the netlist, you should be able to find parasitic resistors linking R0 and the mos gate. If you suspect that the netlisting problem lies with QRC, you can check it using gemini connectivity checker. When enabled, it will short the parasitic resistors and open the parasitic caps so as to check if the input to QRC is still equivalent to the output after the removal of the parasitic devices. You can enable gemini as follows:

    a. Add the following line to your cshrc file:
    setenv DBGRCX_CONNECTIVITY Y

    b. Source the new cshrc file and restart Virtuoso

    c. After running QRC, look at the log file for the results of gemini. If you still have any doubts, please upload the log file as an attachment.

    (Note that gemini is in semi-retired mode. The new checker is pvsnvn but we will not go into that for now)

    Best regards
    Quek

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.