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Monte Carlo simulation for device mismatch

sdineshkumar
sdineshkumar over 10 years ago

I am trying to simulate a SRAM PUF in cadence 5.1. I want to create threshold variations between two back to back connected inverters. I decided to vary threshold of any one of the PMOS . I want to apply monte carlo simulation with guassian distribution to any one of the PMOS. I dont know  how to apply montecarlo variation to a particular PMOS?

Is there any way to do it in virtuoso 5.1

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  • Andrew Beckett
    Andrew Beckett over 10 years ago

    OK, a lot of separate questions here, so let me attempt to answer them in the order you posted them last night:

    Unknown said:
    May I know how to find out the threshold voltage for each MOS after running Montecarlo simulation?

    Perform a dc operating point analysis and then you can access the operating point using a calculator function such as: OP("/M1" "vth"). The M1 is the instance name of the device. If you're using ADE - this will work well. Alternatively, if running spectre from the command line I used this:

    monte montecarlo numruns=10 variations=all {
      dcOp dc
      dcOpInfo info what=oppoint where=file
      models info what=models where=file
    }

    Then I got files, forummc.info.oppoint and forummc.info.models with the data in in human-readable form. My netlist was called forummc.scs, so the prefix of your files would depend on what your input file was called. In the oppoint file I can see vth for each transistor.

    Unknown said:
    This is the spectre code I modified.. When I run this code I am still not getting any variation.. Pls help me..

    There are a couple of things wrong with your file, but neither of these would cause it to not produce variation. The two things wrong are:

    1. NFET (D G S B) cmosn w=w l=l vth0 =0.5+ dvt0/sqrt(l*w)
      This red part is attempting to pass an instance parameter called vth0 to the transistor. This will give a warning in the simulator because vth0 is not an instance parameter of bsim3v3 (I'll explain why in response to your later question)
    2. You have the mismatch variation of dvt0 with the standard deviation set to 100% of the mean value. This means that you'll get quite a few negative values of dvt0 which will generate warnings in the simulator because I don't believe it's supposed to be negative. You probably were just setting it large to try to see a variation?

    Now, even with these mistakes, I still see variation. So my guess is that you've done something wrong in either the circuit netlist or the monte carlo setup. So:

    1. Are your transistors using the model NFET rather than cmosn? If you don't use NFET but use cmosn you'll get the globally defined model without any variation. Your instance lines in your circuit should look like this:
      M1 (D1 G 0 0) NFET w=1u l=0.18u
      M2 (D2 G 0 0) NFET w=1u l=0.18u
    2. Are you running the monte carlo with the variations set to "all" or "mismatch"? If you just set it to "process" you won't see the mismatch variation.

    I also removed the erroneous instance parameter vth0 and reduced the excessive dvt0 variation, and it still worked fine of course (but without the warnings). I also looked at using this:

    statistics {
      process {
        vary vth0 dist=gauss std=9 percent=yes
      }

      mismatch {
        vary vth0 dist=gauss std=4 percent=yes
      }
    }

    That worked well too.

    Unknown said:
    In the file which you have referred they modelled montecarlo using resistors. In the prosess paprameters they have declared mismatch parameter. I am trying to find out the mismatch parameter for the transistor. Can you pls provide a sample code to vary threshold voltage of invereters so that We can follow the same..

    Well, the above shows the principle, but precisely how you should vary the models depends on detailed understanding of the processes themselves. Inventing a threshold variation without any data on measurement is a bit silly - the foundry should have monte carlo models available (I'm assuming the models you've posted may be fictional models because you probably shouldn't have posted them if they belong to a foundry as it would be breaking NDA rules) - so you may be better off obtaining either a real technology from a foundry, or something like gpdk180 from which has monte carlo models for the transistors.

    In addition, understanding more about how mismatch works can be found in papers by Marcel Pelgrom, for example:

    These were from a quick google search for "Pelgrom matching".

    Unknown said:
    Hi, Can you please tell me what is meant by instance parameter?

    If you type "spectre -h bsim3v3" on the command line (or indeed any other component in spectre), you'll see sections listed on instance and model parameters. Instance parameters are those which can be specified on an instance of the device - i.e. where you have:

    M1 (D G S B) nch w=1u l=0.18u ad=...

    These are instance parameters. Whereas model parameters are specified when you define a model - so:

    model nch bsim3v3 type=n vth0=0.4 rsh=0.8 ...

    The parameters here are model parameters.

    Hope this is all clear!

    Regards,

    Andrew.

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  • Tonmoy Dhar
    Tonmoy Dhar over 9 years ago

    Hi Andrew.

    I am also a newbie to the spectre simulation and I am in badly need of your help. I am simulating the following netlist. I see no simulation error. But, I do not see any mismatch variation data in the 'mc1.process.mcdata' file (the file is blank). But, when I run monte carlo simulation with 'variations=process' I see the process variation data inside the 'mc1.process.mcdata' file.  I am working with IC 5.1.41 . Here is the netlist:

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    simulator lang=spectre

    include "45nm_ASU_PTM.inc"

    parameters Ndelvt0 = 0 Pdelvt0 = 0

    subckt NMOS2 (n3 n2 n0 n1)

    parameters Ndelvt0=0

    N0 (n3 n2 n0 n1) nmos l=45n w=45n delvto = Ndelvt0

    simulator lang=spice

    .model  nmos  nmos  level = 14

    +version = 4.0             binunit = 1               paramchk= 1               mobmod  = 0             

    +capmod  = 2               igcmod  = 1               igbmod  = 1               geomod  = 1             

    +diomod  = 1               rdsmod  = 0               rbodymod= 1               rgatemod= 1             

    +permod  = 1               acnqsmod= 0               trnqsmod= 0             

    +tnom    = 27              toxe    = 1.8e-009        toxp    = 1.5e-009        toxm    = 1.8e-009      

    +dtox    = 3e-010          epsrox  = 3.9             wint    = 5e-009          lint    = 0             

    +ll      = 0               wl      = 0               lln     = 1               wln     = 1             

    +lw      = 0               ww      = 0               lwn     = 1               wwn     = 1             

    +lwl     = 0               wwl     = 0               xpart   = 0               toxref  = 1.8e-009      

    +vth0    = 0.62261         k1      = 0.4             k2      = 0               k3      = 0             

    +k3b     = 0               w0      = 2.5e-006        dvt0    = 0       dvt1    = 2             

    +dvt2    = 0               dvt0w   = 0               dvt1w   = 0               dvt2w   = 0             

    +dsub    = 0.1             minv    = 0.05            voffl   = 0               dvtp0   = 1e-010        

    +dvtp1   = 0.1             lpe0    = 0               lpeb    = 0               xj      = 1.4e-008      

    +ngate   = 1e+023          ndep    = 3.24e+018       nsd     = 2e+020          phin    = 0             

    +cdsc    = 0               cdscb   = 0               cdscd   = 0               cit     = 0             

    +voff    = -0.13           nfactor = 1.6             eta0    = 0.0125          etab    = 0             

    +vfb     = -0.55           u0      = 0.049           ua      = 6e-010          ub      = 1.2e-018      

    +uc      = 0               vsat    = 130000          a0      = 1               ags     = 0             

    +a1      = 0               a2      = 1               b0      = 0               b1      = 0             

    +keta    = 0.04            dwg     = 0               dwb     = 0               pclm    = 0.02          

    +pdiblc1 = 0.001           pdiblc2 = 0.001           pdiblcb = -0.005          drout   = 0.5           

    +pvag    = 1e-020          delta   = 0.01            pscbe1  = 8.14e+008       pscbe2  = 1e-007        

    +fprout  = 0.2             pdits   = 0.08            pditsd  = 0.23            pditsl  = 2300000       

    +rsh     = 5               rdsw    = 210             rsw     = 80              rdw     = 80            

    +rdswmin = 0               rdwmin  = 0               rswmin  = 0               prwg    = 0             

    +prwb    = 0               wr      = 1               alpha0  = 0.074           alpha1  = 0.005         

    +beta0   = 30              agidl   = 0.0002          bgidl   = 2.1e+009        cgidl   = 0.0002        

    +egidl   = 0.8             aigbacc = 0.012           bigbacc = 0.0028          cigbacc = 0.002         

    +nigbacc = 1               aigbinv = 0.014           bigbinv = 0.004           cigbinv = 0.004         

    +eigbinv = 1.1             nigbinv = 3               aigc    = 0.015211        bigc    = 0.0027432     

    +cigc    = 0.002           aigsd   = 0.015211        bigsd   = 0.0027432       cigsd   = 0.002         

    +nigc    = 1               poxedge = 1               pigcd   = 1               ntox    = 1             

    +xrcrg1  = 12              xrcrg2  = 5             

    +cgso    = 1.1e-010        cgdo    = 1.1e-010        cgbo    = 2.56e-011       cgdl    = 2.653e-010    

    +cgsl    = 2.653e-010      ckappas = 0.03            ckappad = 0.03            acde    = 1             

    +moin    = 15              noff    = 0.9             voffcv  = 0.02          

    +kt1     = -0.11           kt1l    = 0               kt2     = 0.022           ute     = -1.5          

    +ua1     = 4.31e-009       ub1     = 7.61e-018       uc1     = -5.6e-011       prt     = 0             

    +at      = 33000         

    +fnoimod = 1               tnoimod = 0             

    +jss     = 0.0001          jsws    = 1e-011          jswgs   = 1e-010          njs     = 1             

    +ijthsfwd= 0.01            ijthsrev= 0.001           bvs     = 10              xjbvs   = 1             

    +jsd     = 0.0001          jswd    = 1e-011          jswgd   = 1e-010          njd     = 1             

    +ijthdfwd= 0.01            ijthdrev= 0.001           bvd     = 10              xjbvd   = 1             

    +pbs     = 1               cjs     = 0.0005          mjs     = 0.5             pbsws   = 1             

    +cjsws   = 5e-010          mjsws   = 0.33            pbswgs  = 1               cjswgs  = 3e-010        

    +mjswgs  = 0.33            pbd     = 1               cjd     = 0.0005          mjd     = 0.5           

    +pbswd   = 1               cjswd   = 5e-010          mjswd   = 0.33            pbswgd  = 1             

    +cjswgd  = 5e-010          mjswgd  = 0.33            tpb     = 0.005           tcj     = 0.001         

    +tpbsw   = 0.005           tcjsw   = 0.001           tpbswg  = 0.005           tcjswg  = 0.001         

    +xtis    = 3               xtid    = 3             

    +dmcg    = 0               dmci    = 0               dmdg    = 0               dmcgt   = 0             

    +dwj     = 0               xgw     = 0               xgl     = 0             

    +rshg    = 0.4             gbmin   = 1e-010          rbpb    = 5               rbpd    = 15            

    +rbps    = 15              rbdb    = 15              rbsb    = 15              ngcon   = 1    

    simulator lang=spectre

    ends NMOS2

    subckt PMOS2 (n3 n1 n4 n5)

    P0 (n3 n1 n4 n5) pmos l=45n w=90n delvto = Pdelvt0

    ends PMOS2

    N1 (3 1 0 0) NMOS2 

    N2 (3 2 0 0) NMOS2 

    P1 (3 1 4 5) PMOS2 

    P2 (4 2 5 5) PMOS2 

    vdd 5 0 vsource dc=1.1

    statistics {

    process{

    vary Ndelvt0 dist=gauss std=.3

    vary Pdelvt0 dist=gauss std=.4

    }

    mismatch{

    vary Ndelvt0 dist=gauss std=.3

    }

    }

    mc1 montecarlo variations=mismatch saveprocessparams=yes seed=100 numruns=1{

    mytran tran start=0 stop=10u step=.1u errpreset = conservative

    }

    ---------------------------------------------------------------------------------------------------------------------------------------------------------

    Do you have any suggestion regarding this? Your help will be appreciated. 

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    The problem is that in your subcircuit:

    subckt NMOS2 (n3 n2 n0 n1)
    parameters Ndelvt0=0
    N0 (n3 n2 n0 n1) nmos l=45n w=45n delvto = Ndelvt0

    ...

    The parameters line should not be there. This is masking the global parameter that you have the statistical variation on - and so there ends up being no variation at all within this subcircuit. If you remove this parameters line (or comment it out), then it works as you're expecting (I checked).

    Regards,

    Andrew.

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  • sdineshkumar
    sdineshkumar over 9 years ago

    Hey Andrew,

    I am simulating a SRAM based Physical Unclonable Function. I have few doubts in simulating the PUF.

    I have created 1000 SRAM cells using montecarlo simulation. I am trying to measure the start up behaviour for 20 times. At the beginning, I did ran the simulation for 20 times but I got the same values as the output. In the research paper, it has been mentioned that we have to measure 20 measurements using random seed. So, in cadence, whether we can vary the montecarlo seed number for 20 measurements in order to get the same?

     

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    If you're running monte carlo with 20 runs, then you should get 20 different results. You shouldn't have to mess around with the seed. Normally in ADE XL (say) the seed is a fixed value so that your results are consistent if you run them again, but within the monte carlo itself you should see a range of values.

    If you're not getting that, it implies that either you've got something wrong with your measurement (using the wrong expression can lead to measuring the nominal result every time rather than the varying result) or the statistical models aren't set up correctly. You gave very little information (see the forum guidelines - the first post in each forum to see the kind of info that helps), so it's quite hard to give any suggestions as to what might be wrong. I don't know what version you're using or what your setup looks like.

    Kind Regards,

    Andrew.

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  • sdineshkumar
    sdineshkumar over 9 years ago
    Begin netlist at:    Jan 21 11:07:51 2016
           view name list  = ("lvs" "schematic" "gate_sch" "cmos_sch")
           stop name list  = ("lvs")
           library name    = "lib"
           cell name       = "not"
           view name       = "schematic"
           globals lib     = "basic"
    Loading gpdk180/libInit.il ...
    Loading gpdk180/loadCxt.ile ... done!
    Loading context 'gpdk180' from library 'gpdk180' ... done!
    Loading context 'pdkUtils' from library 'gpdk180' ... done!
    Loading gpdk180/.cdsenv ... done!
    Loading gpdk180/libInitCustomExit.il ... 
    done!
    Loaded gpdk180/libInit.il successfully!
    global error:
    Cannot find switch master cell for instance PM0 in cellView (not schematic) from viewlist 'lvs schematic gate_sch cmos_sch ' in library 'lib'.
    global error:
    Cannot find switch master cell for instance NM0 in cellView (not schematic) from viewlist 'lvs schematic gate_sch cmos_sch ' in library 'lib'.
    si: Netlist did not complete successfully.
    this is the error i am seeing while running LVS with divaLVS.rul. Can you tell How to solve this issue?
    Regards
    Dinesh
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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    For various historical reasons there are two flows in Virtuoso - an analog-centric and a digital-centric flow. Most design kits are set up to use the analog flow, including gpdk180. From the error you've got (which is complaining about not being able to find "lvs" views), you've probably got the "digital" flow enabled; if using the analog flow, it looks for "auLvs" views as it's using the auLvs netlister.

    So, make sure you do:

    setenv CDS_Netlisting_Mode Analog

    (if using csh) or:

    export CDS_Netlisting_Mode=Analog

    (if using bash/ksh) as your shell.

    Do this before you start virtuoso.

    Regards,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 9 years ago

    Also, please follow the Guidelines for the Custom IC Design Forum which clearly ask you not to append on the end of old threads. You've done it more than once now - and this last one was for LVS which was nothing whatsoever to do with Monte Carlo simulation!

    You got lucky this time and your question got answered. However, there's a high likelihood that your subsequent questions will get ignored because they're part of a totally different thread.

    It also makes it very difficult for anyone searching through the forums to find relevant data if there is a mix of completely different subjects in a thread.

    Regards,

    Andrew.

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