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Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in verilog A when they are used in 'if -else statement'

KiranTej

Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in Verilog A 

I think V(P1, T1) <+ 0; would mean voltage difference between node P1 and node T1 is 0 and 

V(P1) <+ V(T1) would mean potential difference between P1 to gnd is equal to T1 to gnd.

I feel these statements kind of means the same, but when I used these statements in 'if block' in 'Verilog A', use of each statement gives different results, can someone please explain what difference does it make between these statements.

Also, can we use these statements in an 'if block'?

  • in reply to KiranTej

    Quite simply, the switch changes position instantaneously - and so the impedance of the switch changes instantaneously. That means there would be a discontinuity in the current through the switch or the voltage across the switch. In the models on the Designer's Guide site, it does at least announce the discontinuity, and that's better than nothing. Circuit simulators don't really like ideal behaviour like this, and a model will work better if it is more realistic about modelling the transition. I'm sure this is covered in Ken and Olaf's book (I don't have a copy with me today so can't give you a reference), and is certainly covered in the Mixed-Signal Methodology Guide that Frank mentioned earlier - it's in the section Analog Best Practices from page 55 onwards.

    Regards,

    Andrew.

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