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parasitic extraction question on sub-blocks using top-level RCE

life

Hi,

If I have a RCE .spf file for a top level cell (for example Cell A) which is comprised of multiple sub-blocks, can I use this same RCE file on simulations where I am only using sub blocks in a test bench? 

To clarify in an example:
Assume the top level cell (Cell A) is comprised of sub-blocks X, Y, and Z, and I only have the parasitic extraction of Cell A (top level). Now let's say I have a new test bench that is only simulating sub-block Y and miscellaneous logic. Can I include this SAME RCE of the top-level Cell A in the .spf files and if so, will Cadence be able to pull the appropriate parasitic data on the nets that I have for sub-block Y? 

  • in reply to ShawnLogan

    Hi Shawn -

    you are right that parasitics and the root causing of the electrical problems created by parasitics is not a function of the simulator.

    Ron Rohrer (the grandfather of SPICE, and of many other developments in EDA) wrote that SPICE was not designed to handle parasitics:

    https://www.linkedin.com/feed/update/urn:li:ugcPost:6726538187788824576?commentUrn=urn%3Ali%3Acomment%3A%28ugcPost%3A6726538187788824576%2C6726865316619677696%29

    There are several tools offered by Cadence (EAD, PAD, ...) or by other vendors (including the one mentioned by Frank) that help understand parasitics, with different degrees of convenience, speed, insight, etc.

    I jumped in to this discussion because the idea and question raised by the topic starter is very sound, very reasonable - and not addressed by the standard flows or tools!

    It's upper hierarchy levels that can wreck a havoc and invalidate your block-level verification.

    The size of the top hierarchy design, with all the parasitics, is sometimes too big for the standard tools.
    The problems caused by the parasitics (IR/EM, timing, signal integrity, matching, etc.), if not captured by the design and verification flow, can be very costly.

    Maxim

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