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Is it possible to do this in VerilogA?

Svilen64

Hi,

Is it possible to compile one part of my verilogA code if an input parameter is set and not compile it when the parameter is not set? Note that this is not like executing a set of commands in an if statement and executing another set if the condition is not satisfied. I am really asking about compiling part of the code if a parameter is set.

Thanks

Svilen

  • Svilen64
    in reply to Svilen64

    Hi Andrew,

    Your approach is doing exactly what I needed. Thanks for the help.

    Svilen

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