Virtuoso SystemVerilog errors

Hi,

I am using Virtuoso for AMS simulations with SystemVerilog modules. The modules are not stored in the cellview-folder itself (e.g. cell-name is "tbKernel")  - instead they are in another folder of an SVN working copy. To access those SVN files from the Virtuoso Libmanager, I created symbolic links from the cellview folder "./tbKernel/systemVerilog" to the SVN - e.g. "./tbKernel/systemVerilog/verilog.sv --> ../../svn/testbench/tbKernel.sv". This is working fine for a simple SV module !

Another (more complex) SV file imports modules and packages, some are located in the same SVN folder, others are standard packages such as "cmath". Since the SV files are typically simulated in another environment than Virtuoso (e.g. Questasim), I am sure the syntax is correct and working properly in the other environment.

The "check&save" for this more complex SV file shows the following errors:

 22 package cmath;
 23 import "DPI-C" function real sin(input real x);
 24 endpackage // cmath

 26 import cmath::*;                                   <-- ERROR-1: Package cmath cannot be bound !

 28 // import tbObjPkg::*;                           <-- ERROR-2: Package tbObjPkg cannot be bound !
 29 `include "/...some_path_here.../svn/testbench/tbObjPkg.sv"  <-- absolut path fixes ERROR-2, but is not a solution - I need relative pathes to keep consistency in the SVN for other environments.

799 //always @ (*) begin                           <-- ERROR-3: Using "*" grays out the rest of the code until the next "*" 
800 always @ (/*AUTOSENS*/) begin      <-- this fixes ERROR-3
801 if (sdEnable==1) begin
802 sdin1 = sdInterface1.sdout_sd;

Now my questions on those errors are:

ERROR-1: This is a package that comes with the tool - how can I make it available and bind it in Virtuoso - is there a dedicated entry in the "hdl.var" file required (we are using XCELIUM for AMS simulations) ?

ERROR-2: How can I make the tool looking in the same folder (relative pathes) for modules/files to be included - especially with my linked "verilog.sv" to the SVN folder ?  

ERROR-3: Why does "*" work in the pure digital environment (e.g. questasim) but not in the Virtuoso environment ?

Thanks in advance for some suggestions !