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VerilogA module in a crystal oscillator simulation testbench negatively affects simulation parameters for oscillation

David Mulvihill

Hello, 

I'm running a transient analysis of a high-Q crystal oscillator along with a verilogA module that I wrote that mimics the controlling digital logic.  While I regularly use AC, harmonic balance and hbnoise analyses for many parameters, this particular analysis requires transient to analyze some closed loop response with the controlling digital logic.

For many years I've used this article for transient analysis with crystal oscillators:

https://community.cadence.com/cadence_blogs_8/b/rf/posts/mmsim12-1-speed-up-transient-analysis-of-crystal-oscillators

While some settings in the article are deprecated now, I still use:

  • CX preset in Spectre X
  • traponly integration method
  • alllocal accuracy parameter
  • maxstep of 1/20 of the oscillator period

When the oscillator control inputs are stimulated with vpwl and vdc sources, the oscillator behaves as expected (oscillation is still growing):

But when I add the verilogA module in to the testbench, even if I keep the oscillator inputs connected to the same vpwl/vdc sources, the oscillation dies when enabled.  Note - a vpulse source is used to drive the clock input to the verilogA digital logic, but the outputs of that verilogA module are not connected to the circuit in question.

If I decrease the maxstep size substantially, oscillation grows again. I haven't exhaustively searched for where it breaks, but 1/50 of the oscillator period does not work, but 1/500 does.

Finally and maybe most interestingly, if I disconnect the vpulse source driving a clock to the verilogA module, I can go back to a maxstep of 1/20 of the oscillator period!

Are there other settings to prevent this from happening? As you can imagine, setting maxstep to 1/500 of the oscillator period substantially increases simulation time.  I've tried changing reltol and abstol settings, but not surprisingly, it's not helping that much, can have negative effects and is slowing down the simulation far more than constraining the maxstep size does.

Virtuoso version: ICADVM20.1-64b.500.27.EHF11746

Spectre version: 21.1.0.582.isr14

Thank you in advance!

  • in reply to Andrew Beckett

    Dear Andrew,

    Thank you again for reading my comments and adding your insight! Please allow me two comments.

    Andrew Beckett said:
    For a start, the gear2only and traponly are slight misnomers - I always thought they should be called gear2mostly and trapmostly (!), because at breakpoints (such as the start/end of a transition in a voltage source or Verilog-A transition) it will always switch to euler for that time step

    I understand this from the Cadence documentation. My understanding, rightly or wrongly, is that the choice of the "gear2only" algorithm will utilize gear2 as the dominant algorithm and to a greater extent than specifying "gear2".

    I am also well aware of the numerical damping the algorithm provides. However, this is easily overcome by a sustaining amplifier and its resonator with a reasonably robust design. In fact, if the algorithm is responsible for damping out an oscillation, it is probably a very good clue the design is not sufficiently robust! With respect to David's problem, I would think it would help the convergence as the integration seems to be overly sensitive to clock transitions. My personal experience, and I will only speak for myself, is that "gear2only" has provided the most robust convergence simulation results.

    Andrew Beckett said:

    This is unlikely to help either, for two reasons:

    1. The output of the voltage source is still in the matrix and needs to be solved for, and so the sharp transition is still present

    Having written a numerical integration algorithm many years ago, it seems to me the difficulty in a numerical algorithm converging on an ideal source with a discontinuity driving a series resistor [1] and it driving an arbitrary load impedance is significant. I have not experienced any integration issues when an ideal source drives a purely resistive load whose resistance value is reasonable. This was the motivation for my suggestion to David.

    If the Cadence algorithm reverts to a first-order integration algorithm in this case, I am surprised, but will accept your answer !

    Shawn

    [1] i.e., a state voltage is not involved

  • in reply to ShawnLogan
    ShawnLogan said:
    I understand this from the Cadence documentation. My understanding, rightly or wrongly, is that the choice of the "gear2only" algorithm will utilize gear2 as the dominant algorithm and to a greater extent than specifying "gear2".

    This is covered in A.3.3.7 (page 352) of Ken Kundert's A Designer's Guide to SPICE and Spectre.

    ShawnLogan said:
    I am also well aware of the numerical damping the algorithm provides. However, this is easily overcome by a sustaining amplifier and its resonator with a reasonably robust design.

    Of course, but given that the oscillation was already being attenuated, gear2only will only make that worse. In general, gear2only often gives the best bang for the buck, but trapezoidal generally will give the best accuracy - but sometimes the presence of trapzoidal ringing can cause a bigger problem - so there's always a tradeoff.

    ShawnLogan said:
    If the Cadence algorithm reverts to a first-order integration algorithm in this case, I am surprised, but will accept your answer !

    This is covered in section 4.2.1 and 4.2.2 of Ken's' book (pages 131 onwards).

    Andrew

  • in reply to Andrew Beckett

    Thank you, Andrew, for taking the time to read my comments, respond and include your references.

    Shawn

  • in reply to ShawnLogan

    Hi folks, I've submitted a ticked for cadence support and am getting traction there, but I felt I should post another finding.

    The older documentation on crystal oscillator settings recommended reltol=1e-3, vabstol=1e-6, prior to errpreset modification.  The newer documentation suggests reltol=1e-4, vabstol=1e-7.  sweeping these settings, with maxstep = 1/20 osc period:

    • reltol=1e-3, vabstol=1e-6: old default, dampening oscillation
    • reltol=1e-4, vabstol=1e-6: no change
    • reltol=1e-4, vabstol=1e-7: no change
    • reltol=1e-3, vabstol=1e-7: significant benefit in reducing oscillation dampening, but it's still present:

    this does seem better from a run-time perspective vs. reducing maxstep, but I'm still discussing with cadence support.

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