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problem with figs~>lpps~>layerName

ToMWUT
Hello,

I have such a problem with my SKILL code and design:

My code looks like this

cv=geGetWindowCellView(window(3))

printf("\nALL LPPS (Layer purpose pair) \n")

; Here I want to check what LPPS I have in my design

;

for( i 0 length(cv~>lpps~>layerName)-1

printf( "LPP name: %s purpose %s \n", nth(i

cv~>lpps~>layerName), nth(i cv~>lpps~>purpose))

);for

printf("\n Figures belongs to LPPS \n")

print(cv~>nets~>figs~>lpps~>layerName)cv=geGetWindowCellView(window(3))

printf("\nALL LPPS (Layer purpose pair) \n")

for( i 0 length(cv~>lpps~>layerName)-1

printf( "LPP name: %s purpose %s \n", nth(i

cv~>lpps~>layerName), nth(i cv~>lpps~>purpose))

);for

; Here I'd like to check if all figs belongs to appropriate LPPS (2)

;

printf("\n Figures belongs to LPPS \n")

print(cv~>nets~>figs~>lpps~>layerName)

The problem is that in (2) I get an empty list (nil)

The result of the above code looks like this:

ALL LPPS (Layer purpose pair)

LPP name: pin purpose drawing

LPP name: device purpose drawing

LPP name: PO1 purpose drawing

LPP name: ME1 purpose drawing

Figures belongs to LPPS

(nil nil nil nil nil nil nil nil nil nil nil nil nil nil nil nil nil nil nil)

Why is it so? Does anyone have any ideas?
Parents

  • Thanks once again Andrew,

    You where right about two things: first of all you're right that you don't have any data about my design, so I've decided to put a screen shot with it, so you can have a look.

    http://home.elka.pw.edu.pl/~tscislo/layout.jpg

    This is a very simple design which was extracted from layout using Assura extraction tool. This is a NAND cell.

    The second thing about which you were right was that I have a problem with routing, because when I execute:

    cv~>nets~>figs I get nils

    But the problem after the extraction process is that you can actually see the nets on the layout, so I have no idea why the Cadence data base has no information about the figures...

    Thanks,

    ToM.

     
Reply

  • Thanks once again Andrew,

    You where right about two things: first of all you're right that you don't have any data about my design, so I've decided to put a screen shot with it, so you can have a look.

    http://home.elka.pw.edu.pl/~tscislo/layout.jpg

    This is a very simple design which was extracted from layout using Assura extraction tool. This is a NAND cell.

    The second thing about which you were right was that I have a problem with routing, because when I execute:

    cv~>nets~>figs I get nils

    But the problem after the extraction process is that you can actually see the nets on the layout, so I have no idea why the Cadence data base has no information about the figures...

    Thanks,

    ToM.

     
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