How do I avoid the renaming of long net names during netlisting/flattening?

I've been able to read a Verilog file into DFII via ihdl to create a netlist view. My intent is to create an autoLayout view, so I go to "Tools --> Floorplan/Netlist in my window that shows me the netlist view and then go to the Hierarchy Browser. After preparing all my settings I click on "Hierarchy ---> Generate Physical Hierarchy". Eventually I get my autoLayout view.

Everything seems hunky-dory, except that some nets have gotten renamed to something like "_LoNgNeTnAmE108(123)". It appears the flattener didn't like the original net name (even though it's not really that much longer and I don't think there are restrictions on net names in the CDBA, or maybe it's 256 bytes but I'm nowhere near that length).

The problem now is that I can't correlate some of my nets in the Verilog netlist with the nets in my floorplan.

I haven't found any documentation on net renaming or the generation of a mapping file that would help me sort this out. There's nothing to be found in the adpFlatten directory that I could take advantage of.

Any comments what else I could try to remedy this problem? I need my symbolic netlist match exactly my Verilog netlist. BTW, my netlist is flat. In other words, there is no hierarchy involved. It's just a bunch of blocks (represented by abstracts) interconnected by a bunch of nets. 

The DFII version I'm using is IC5.1 on Solaris (Sparc V9).