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How do I avoid the renaming of long net names during netlisting/flattening?

skillet

I've been able to read a Verilog file into DFII via ihdl to create a netlist view. My intent is to create an autoLayout view, so I go to "Tools --> Floorplan/Netlist in my window that shows me the netlist view and then go to the Hierarchy Browser. After preparing all my settings I click on "Hierarchy ---> Generate Physical Hierarchy". Eventually I get my autoLayout view.

Everything seems hunky-dory, except that some nets have gotten renamed to something like "_LoNgNeTnAmE108(123)". It appears the flattener didn't like the original net name (even though it's not really that much longer and I don't think there are restrictions on net names in the CDBA, or maybe it's 256 bytes but I'm nowhere near that length).

The problem now is that I can't correlate some of my nets in the Verilog netlist with the nets in my floorplan.

I haven't found any documentation on net renaming or the generation of a mapping file that would help me sort this out. There's nothing to be found in the adpFlatten directory that I could take advantage of.

Any comments what else I could try to remedy this problem? I need my symbolic netlist match exactly my Verilog netlist. BTW, my netlist is flat. In other words, there is no hierarchy involved. It's just a bunch of blocks (represented by abstracts) interconnected by a bunch of nets. 

The DFII version I'm using is IC5.1 on Solaris (Sparc V9).

Parents
  • I can't get it to work. I've tried our latest Solaris version (sub-version 5.10.41_USR6.127.29) and I tried our latest Linux version (also sub-version 5.10.41_USR6.127.29). I've tried 64b and 32b versions. Neither the GUI-based nor the standalone versions work. I've put most of my hope into the standalone version as I at least know that it reads my parameter file where I can explicitely state
    max_net_name_length := 4000
    Note that you stated in your last post
    maxNetNameLength := 4000
    but according to the Cadence documentation it should be the former expression. Just to be sure, I tried your expression as well but it isn't accepted by ihdl.

    I use the following command and data files with the purpose to create a netlist view:
    command:
    ihdllnx86 -f ihdl_files -p paramFile <topRTL>.v
    paramFile:
    dest_sch_lib := <destLibName>
    ref_lib_list := basic, <    otherLibs>
    import_if_exists := 1
    import_cells := 0
    import_lib_cells := 0
    structural_views := 6
    schematic_view_name := schematic
    functional_view_name := functional
    netlist_view_name := netlist
    symbol_view_name := symbol
    log_file_name := ./verilogIn.log
    map_file_name := ./verilogIn.map.table
    work_area := /home/<    user>/verilogIn
    power_net := vdd
    ground_net := vss
    create_map_table := 1
    max_net_name_length := 4000
    sheet_symbol := Asize
    page_row_limit := 512
    page_col_limit := 256
    label_height := 12
    line_line_spacing := 0.2
    line_component_spacing := 0.5
    density_level := 0
    client := synthesis
    alias_module := cds_alias
    cont_assign_symbol := basic patch symbol
    I don't see any other avenue to get this to work. No matter what approach I use on Solaris, it always dies with a segmentation fault.

Reply
  • I can't get it to work. I've tried our latest Solaris version (sub-version 5.10.41_USR6.127.29) and I tried our latest Linux version (also sub-version 5.10.41_USR6.127.29). I've tried 64b and 32b versions. Neither the GUI-based nor the standalone versions work. I've put most of my hope into the standalone version as I at least know that it reads my parameter file where I can explicitely state
    max_net_name_length := 4000
    Note that you stated in your last post
    maxNetNameLength := 4000
    but according to the Cadence documentation it should be the former expression. Just to be sure, I tried your expression as well but it isn't accepted by ihdl.

    I use the following command and data files with the purpose to create a netlist view:
    command:
    ihdllnx86 -f ihdl_files -p paramFile <topRTL>.v
    paramFile:
    dest_sch_lib := <destLibName>
    ref_lib_list := basic, <    otherLibs>
    import_if_exists := 1
    import_cells := 0
    import_lib_cells := 0
    structural_views := 6
    schematic_view_name := schematic
    functional_view_name := functional
    netlist_view_name := netlist
    symbol_view_name := symbol
    log_file_name := ./verilogIn.log
    map_file_name := ./verilogIn.map.table
    work_area := /home/<    user>/verilogIn
    power_net := vdd
    ground_net := vss
    create_map_table := 1
    max_net_name_length := 4000
    sheet_symbol := Asize
    page_row_limit := 512
    page_col_limit := 256
    label_height := 12
    line_line_spacing := 0.2
    line_component_spacing := 0.5
    density_level := 0
    client := synthesis
    alias_module := cds_alias
    cont_assign_symbol := basic patch symbol
    I don't see any other avenue to get this to work. No matter what approach I use on Solaris, it always dies with a segmentation fault.

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