layout size estimate based on schematic

Hi guys,

i'm looking to use Skill to calculate the total active area & resistor area down the hierarchy of the schematic and allow me to make a initial guess at layout area, by adding in a fudge factor based on previous chips. 

The flow i have in my mind is find every device type on my list (e.g nmos1, pmos1, res1, nmos_high_voltage....etc) then for each isntance arrive at an area by doing "W x Lx Fingers x Multiples=Area", then adds these all together to get a total area.

The complication's i can forsee are:

units: for example if one parameter is in um and another in nm, i'd need to standardise

hierarchy: so far i can get W & L at the top  level of the schem but not down the hierarchy. Also how do i handle cell repition or even multiple instances of the same cell using the Intsance_name<0:9> as a quick way to represent 10 same type symbols.

resistors: they don't have the "F" fingers parameter, don't want the Skill to fall over due to this.

Any guidance is glady received

Thanks

Stu