how to re-evaluate the pcell submaster

Why do you need to reevaluate it? Pcell evaluation is triggered by a change of parameters which results in a new variant (submaster) being required. Also, redefinition of the pcell supermaster will also re-trigger the recreation of all variants in use.

If  you purge the supermaster, that would also cause them to be reevaluated. However, normally this should not be needed. The danger is if you have a pcell which depends on dynamic data outside of the parameters - if you're doing that, then that is bad design of the pcell.

Perhaps if you can explain why you need this, it would help understand your requirements.

Regards,

Andrew.

 We define the Pcell by the python plug-in. The python scripts geneate the pcell in OpenAccess format. We expect each time we instaniate this pcell in virtuoso layout view, the python scripts will be called. However, we found if we set  new parameters for this pcell, no problem, python scripts will be called. However, if we use the parameters  which has alread been set (which means submaster has been created in memory), python scripts will not be called. That's why I am worndering if refreshing the submaster can help.

 Also I found in the manuel that the "Express Pcell" might help. But I haven't succeeded to lauch the express pcell window. Probably I set the wrong enviorement parameters.

 Thanks for your replying, Andrew.

Probably the only solution is to close the pcell cellViews (File->Close Data) or ask Ciranova (since it's their plugin, I presume).

Cadence does not support non-SKILL pcells, so it's very hard for me to give advice. I don't think Express pcells will work with non-SKILL pcells.

Regards,

Andrew.

Why would you want the Python code to run again? If you are placing the exact same parameters of another instance, Virtuoso runs much faster because it does not have to re-evaluate the pcell. In this case it uses a common "sub-master" for that pcell. Say for example you have a complex inverter pcell that takes 1 second to evaluate the Python code that constructs it. If you place the same inverter size 100 times on your design, re-running your Python code every time will take 100 seconds. If the code is only evaluated once and the sub-master is rereferenced for sub-sequent placments, your total evaluation time is only 1 second.

Even if the Express Pcell caching worked with your pcells, this would only make your problem worse. The way the Express Pcell feature works for Skill pcells is that it saves your evaluated sub-master to disk, so the next time you open your design the code isn't run at all. The saved pcell that was evaluated in the last session is read in from disk. In this case, once the cache was built, assuming no new pcells are added, there would be no Skill code run at all. It sounds like your goal is to run the code more than necessary.

Derek

 Derek,

My guess was that the code was referencing some data outside of the parameters, which was changing.

This is bad design of a pcell. It's OK to reference static data (e.g. info from the tech file), but referencing some data which may change during a session is not safe - all communication should be via the pcell parameters - as that will trigger pcell re-eval where necessary.

Or maybe it's that the pcells are being developed and the code is being changed. If it was SKILL code, this is handled automatically - if you redefine the pcell, it triggers a re-eval of all variants - and in IC614 you can use the SKILL Development Environment to single step through your pcell code, reload it, and see the effect of changes. But I wouldn't know how to force any python code to get re-loaded.

Regards,

Andrew.