Hierarchically Layer generation

 Hi Zach,

Just to address some of the points:

1) This code can be used with IC61x (I just tried it, it worked as I expected), even though it was written and tested with the IC5141 release.

2) CCShierLayerOps.il is not a function, it is the file that contains functions such as CCShiHierLayerOps(), CCShierLayerOps() and others.

3) It might do, because, as Andrew pointed out, there might be an alternative approach that turns out to be more efficient.

4) I've not seen much discussion about hardware used on this forum, but it is a relevant question - if the processor is a recent multi-core, versus, say, an older processor architecture.

5) Design complexity might be more of a factor than hierarchy depth, but it is difficult to say, although I wrote the code, I did not test it under a large array of possible scenarios and designs.  Unlike Cadence R&D I do not have any regression tests or data at my disposal.

6) Since the code is generic, but the operation of it is very design dependent, it is highly unlikely that anyone reading the forum would have an idea as to how long it might take to run this code on your design, on your hardware etc.

I am glad that you were able to get the code to work as you needed.  As noted above, I am the author of that particular piece of SKILL code, so I have a vested interest in it; I wrote it to perform a task that was not available from the virtuoso menus. I hope that you and others continue to find it helpful.

Regards,

Lawrence.

 Hi Zach,

Just to address some of the points:

1) This code can be used with IC61x (I just tried it, it worked as I expected), even though it was written and tested with the IC5141 release.

2) CCShierLayerOps.il is not a function, it is the file that contains functions such as CCShiHierLayerOps(), CCShierLayerOps() and others.

3) It might do, because, as Andrew pointed out, there might be an alternative approach that turns out to be more efficient.

4) I've not seen much discussion about hardware used on this forum, but it is a relevant question - if the processor is a recent multi-core, versus, say, an older processor architecture.

5) Design complexity might be more of a factor than hierarchy depth, but it is difficult to say, although I wrote the code, I did not test it under a large array of possible scenarios and designs.  Unlike Cadence R&D I do not have any regression tests or data at my disposal.

6) Since the code is generic, but the operation of it is very design dependent, it is highly unlikely that anyone reading the forum would have an idea as to how long it might take to run this code on your design, on your hardware etc.

I am glad that you were able to get the code to work as you needed.  As noted above, I am the author of that particular piece of SKILL code, so I have a vested interest in it; I wrote it to perform a task that was not available from the virtuoso menus. I hope that you and others continue to find it helpful.

Regards,

Lawrence.