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Nor Gate

CHECKMATE

I am designing a simple two input NOR gate in cadence.

But the problem is when I do LVS of my NOR gate it gives me an error.

Since the NOR gate is designed with two PMOS in series and two NMOS in parallel.

I used Number of fingers equal to 2 for both pmos and nmos properties and set Number of fingers equal to 1 as well for both

I have attached my schematic and layout screenshots.

In the Assura LVS report:

======================================= 

Under the Matched Instances with Bad Net Connections

=========================================

Schematic Instance: MN1_enm

Layout Instance: avD62_1 n

Pin                     SchNet                  LayNet

S                          GND                     Out

D                           Out                      GND

 

Looking at this it seems my Nmos in parallel for a NOR gate are not merging.Is there a way I can solve this problem.

 Thanks for your help....but this is a weird error.

 

  • It looks from the error as if the S and D pins have not been set to be permutable. There are several places this would be done - one in the extract rules themselves (e.g. on the extractMOS or extractDevice statements). That takes care of the extraction side. On the schematic side, it can be done in the auLvs part of the CDF. Also there's various functions (e.g pinSwap) in the avCompareRules which can used to do this kind of thing.

    I think in practice to debug it, you'd be best to contact customer support (sorry if I keep advising this, but it is there for a reason) so somebody can work through with you what could be wrong. It's hard to diagnose without more of the data.

    Best Regards,

    Andrew.

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