Stats

  • Locked Locked
  • Replies 1
  • Subscribers 143
  • Views 12875
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How do I verify my pcells in LVS and DRC?

VaughnR

I am or have been for a year now. Creating and updating old pcells. In my last batch of fixes I unknowing broke a Nor after three legs. Can you describe to me how you would verify your pcells to find these unfortunate situations?

I am hoping for some kind of skill that would array pcells by varing sizes and turn on or off their parameters. Then also create a schematic or netlist that I can LVS to.

 

  • I've written SKILL code to do this kind of thing in the past - just a matter of placing down instances and hooking them up, and then running DRC and LVS on them, as you say. Takes a bit of thought, in order to ensure it's routed correctly, but even doing simple things like placing pins over the instance pins in the layout can be a good start.

    Cadence has a tool, STEP, for doing this kind of automated testing, so you might want to talk to your local Cadence office for more details.

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.