VXL pin generation of inherited nets

Dear all, 

I have already looked into Solution ID: 1833291 but it does not seem to help me. 

I would like to know  how top level schematic nets that are

 1. not connected to any pins ( in top level )
 2. inherited in lower level schematic( inherited connection)

 treated during VXL pin generation. 

I have a net Xsub in the top level connected to a R  instance terminal . This  net is used by one of the lower level schematics. The netSet property was set in the top level and the netexpression property was defined in the lower level schematic. A Check&Save shows no errors ( and this probably indicates the net expression resolved properly and the lower level schematic knew that the net is defined in the top level)

In IC613 VXL mode,  Xsub does _not_ show up in the pin list (schematic Navigator panel in the left) . Yet in the Generate Layout prompt (VXl->Generate from Source ) , the net shows up in the  pin list.

I am aware that the one can disable pin creation by selecting the  pin and unchecking the Create checkbox. 

Why does VXL by default create a layout pin for a net in the top level when it knows that it has no schematic pin connected to it and that it is inherited?