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Verilog-A to .lib transition

eppo

 Hi All,

I have wrote Verilog-A transistor model and want to perform simulation with tabular method. For this, I need to convert my model to .lib file to improve simulation time.

 Anyone have an idea to do this.

 Thanks,

Regards 

 

  • Andrew Beckett

    I have no idea what a .lib file for a transistor would mean. .lib is for defining timing and loading effects for standard cells and other logic blocks - see http://www.opensourceliberty.org/

    So I'm not sure what your question means.

    Andrew.

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