How to create(using) parasitic report by using Cadence ADEXL

 
 Hi, to whom it maybe helpful, we have some issues with the parasitic-aware design flow.

We are using Cadecen IC 6.1.4.500.6 (32-bit) + Assura 410 + EXT913 + mmsim7.11.188
The designkits we are using is IBM 0.13umCMOS--cmrf8sf(V1.8.0.4DM).

The initial DRC/LVS/QRC is fine. Also, we can use the ADEXL to create an estimated parasitic file. Meanwhile, by using parasitic report, the extraced and estimated parasitic components(C/L/K) can be viewed net by net, terminal to terminal.. etc.


The trouble is we can not enable the "R reporting " functions. Also, we can not use the parasitic "compare" functions.

It seems both of these two functions require a DC simulation running in advance. and we do have run two DC simulations(save DC operating point) under the same ADEXL enviroment by choosing the design-view to estimated and extracted, respectively.

However, after DC simulation, nothing changed and we still unable to using the "R reporting "  and "parasitic compare" functions.

Any suggestion would be really appreciated.Maybe I missed some stages.
thanks in advance.