I've written a nicely scaleable VerilogA module using multi-line busses for the ports and internal 'FOR' loops all parameterized with a pre-processor macro to set the number of ports. The code works nicely, I can set the macro to arbitrary positive values and the module compiles and runs fine.
However, at the moment, I can only set the macro by edding some VerilogA code. Ideally, I would like to define the number of ports as a CDF parameter and pass it down to my module. But as a pre-processor variable is not a standard module parameter, I was not able to find instructions on how to set it from the CDF... Can this be done ?
I have the impression that a good way would be to create a PCell that generates VerilogA views on the fly. Is that possible ? I have already played extensively with PCells generating schematics and symbols -- what about text views or VerilogA ? It seems it is not a support view type in the pcDefinePCell() arguments list...In this fashion each submaster would define a unique module (the nbr of ports would be in the list of formal parameters) which would come in very handy to manage varoius instances of my module with different port numbers...
I did not try this out yet -- would like to understand if that is feasible...
Could you provide the Solution ID?