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How to pass a value to a pre-processor macro in a VerilogA view from CDF ?

Herge

Hello,

I've written a nicely scaleable VerilogA module using multi-line busses for the ports and internal 'FOR' loops all parameterized with a pre-processor macro to set the number of ports. The code works nicely, I can set the macro to arbitrary positive values and the module compiles and runs fine.

 However, at the moment, I can only set the macro by edding some VerilogA code. Ideally, I would like to define the number of ports as a CDF parameter and pass it down to my module. But as a pre-processor variable is not a standard module parameter, I was not able to find instructions on how to set it from the CDF... Can this be done ?

I have the impression that a good way would be to create a PCell that generates VerilogA views on the fly. Is that possible ? I have already played extensively with PCells generating schematics and symbols -- what about text views or VerilogA ? It seems it is not a support view type in the pcDefinePCell() arguments list...
In this fashion each submaster would define a unique module (the nbr of ports would be in the list of formal parameters) which would come in very handy to manage varoius instances of my module with different port numbers...

I did not try this out yet -- would like to understand if that is feasible...

 Thanks.

Parents

  • Herge entered a support request, I (wrongfully) presumed this would results in a solution.

    I have a similar problem: I want to make a binary to thermometer decoder and I want the number of outputs ports to be a CDF parameter. This presents two problems.

    1. In verilog-A the number of output ports must be set by 'define statement.
    2. I have to regenerate the symbol everytime I change the number of ports. This can be solved by using a pcell symbol.
    Would it be possible to add a callback function to the CDF parameter (number of ports), and let the callback edit the define statement in the verilog.va file? (I think this solution does not require a private SKILL function.)
Reply

  • Herge entered a support request, I (wrongfully) presumed this would results in a solution.

    I have a similar problem: I want to make a binary to thermometer decoder and I want the number of outputs ports to be a CDF parameter. This presents two problems.

    1. In verilog-A the number of output ports must be set by 'define statement.
    2. I have to regenerate the symbol everytime I change the number of ports. This can be solved by using a pcell symbol.
    Would it be possible to add a callback function to the CDF parameter (number of ports), and let the callback edit the define statement in the verilog.va file? (I think this solution does not require a private SKILL function.)
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