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How to pass a value to a pre-processor macro in a VerilogA view from CDF ?

Herge

Hello,

I've written a nicely scaleable VerilogA module using multi-line busses for the ports and internal 'FOR' loops all parameterized with a pre-processor macro to set the number of ports. The code works nicely, I can set the macro to arbitrary positive values and the module compiles and runs fine.

 However, at the moment, I can only set the macro by edding some VerilogA code. Ideally, I would like to define the number of ports as a CDF parameter and pass it down to my module. But as a pre-processor variable is not a standard module parameter, I was not able to find instructions on how to set it from the CDF... Can this be done ?

I have the impression that a good way would be to create a PCell that generates VerilogA views on the fly. Is that possible ? I have already played extensively with PCells generating schematics and symbols -- what about text views or VerilogA ? It seems it is not a support view type in the pcDefinePCell() arguments list...
In this fashion each submaster would define a unique module (the nbr of ports would be in the list of formal parameters) which would come in very handy to manage varoius instances of my module with different port numbers...

I did not try this out yet -- would like to understand if that is feasible...

 Thanks.

Parents

  • Indeed, I am not yet aware of a solution allowing to have a PCell that netlists to an underlying scaleable VerilogA module.

    What was solved in the above conversation was the question on how to pass a CDF parameter value to a VerilogA pre-processor macro. The method applied in rfLib allows indeed to set pre-processor macro's from CDF parameters, but this is not sufficient to enable a variable number of ports on the VerilogA module during netlisting. 

    The netlister checks the terminals on the VerilogA view which was set when the view was checked & saved (so using the default number of ports, not the actual one set in CDF).  Despite the fact that I have a schematic PCell implementing the correct (dynamic) number of ports, I can not prevent at the moment the netlister to query the (frozen) verilogA view data. I have put a support request (Case# 45438804) on that.

     

     

Reply

  • Indeed, I am not yet aware of a solution allowing to have a PCell that netlists to an underlying scaleable VerilogA module.

    What was solved in the above conversation was the question on how to pass a CDF parameter value to a VerilogA pre-processor macro. The method applied in rfLib allows indeed to set pre-processor macro's from CDF parameters, but this is not sufficient to enable a variable number of ports on the VerilogA module during netlisting. 

    The netlister checks the terminals on the VerilogA view which was set when the view was checked & saved (so using the default number of ports, not the actual one set in CDF).  Despite the fact that I have a schematic PCell implementing the correct (dynamic) number of ports, I can not prevent at the moment the netlister to query the (frozen) verilogA view data. I have put a support request (Case# 45438804) on that.

     

     

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