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How to trigger VerilogA syntax checker and parser using SKILL?

Zhimiao Chen

 Hi, all,

 I am now wring a tool to generate VerilogA model, but failed to integrate it into the cadence environment with meaningful cell view. (that means: dbOpenCellViewByType(libName cellName "veriloga") == nil).The possible reason is that the generated veriloga code is not checked and parsed. Can cadence skill trigger a syntax checker and parser?

 

Thanks!

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  • skillUser

    Hi,

    I think that you want to run the schInstallHDL() command on the Verilog syntax file to "install" it as a verilog view of a cell in a library.  Nothe that this is not the same as running Verilog In - the latter approach can be used to build schematics of the hierarchy described in the Verilog file, but the schInstallHDL method (I think) just does one level of hierarchy in the Verilog file.

    Hope this helps.

    Lawrence.

Reply
  • skillUser

    Hi,

    I think that you want to run the schInstallHDL() command on the Verilog syntax file to "install" it as a verilog view of a cell in a library.  Nothe that this is not the same as running Verilog In - the latter approach can be used to build schematics of the hierarchy described in the Verilog file, but the schInstallHDL method (I think) just does one level of hierarchy in the Verilog file.

    Hope this helps.

    Lawrence.

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