• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC SKILL
  3. dummy device finder

Stats

  • Locked Locked
  • Replies 6
  • Subscribers 144
  • Views 17099
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

dummy device finder

varunkumar
varunkumar over 12 years ago
Can you send me a skill code to find the Dummy devices (MOS,RESISTOR etc) in layout 
  • Cancel
Parents
  • Andrew Beckett
    Andrew Beckett over 12 years ago

    That's not going to be so easy then. I had thought you might be able to do:

    lceExtract(cvId) ; to use the Virtuoso Layout Suite XL extractor
    dummies=setof(inst cvId~>instances
      firstNet=car(inst~>instTerms)~>net
      firstNet && forall(instTerm cdr(inst~>instTerms) instTerm~>net==firstNet)
    )

    But even that's not quite right. The problem is that lceExtract will probably not work in general if there's no schematic source, or on partly laid out designs. 

    Fundamentally you're going to have to extract the connections from the device and see whether the nets are all the same for all instTerms - something like that. If it had been done with layout XL, something like the above would be relatively straightforward (it would need some refinement to ensure that all the instTerms are actually present).

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Andrew Beckett
    Andrew Beckett over 12 years ago

    That's not going to be so easy then. I had thought you might be able to do:

    lceExtract(cvId) ; to use the Virtuoso Layout Suite XL extractor
    dummies=setof(inst cvId~>instances
      firstNet=car(inst~>instTerms)~>net
      firstNet && forall(instTerm cdr(inst~>instTerms) instTerm~>net==firstNet)
    )

    But even that's not quite right. The problem is that lceExtract will probably not work in general if there's no schematic source, or on partly laid out designs. 

    Fundamentally you're going to have to extract the connections from the device and see whether the nets are all the same for all instTerms - something like that. If it had been done with layout XL, something like the above would be relatively straightforward (it would need some refinement to ensure that all the instTerms are actually present).

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information