when I do lvs verification, the one I hate most is the short causing by floating vias in sub block(sub block is lvs/drc cleaned), especially
the sub-block has irregular shape (like a squid, spreading out all over to other blocks, for example, clock buffers..). I wonder if someone
can write a skill code to find floating vias in layout (floating vias means vias not connected to any nets or any instances).
I'm using cadence ic615.06.15.151
Are you using Virtuoso Layout XL? Without that, this is going to be pretty difficult - otherwise you're going to have to extract the connectivity somehow. With Layout XL this would be pretty trivial.
That said, I suspect you're not, because otherwise you probably wouldn't have the LVS problems...
I'm not entirely sure what you mean though - maybe a picture of an example would help? (use the Options tab to upload a picture when replying).