when I do lvs verification, the one I hate most is the short causing by floating vias in sub block(sub block is lvs/drc cleaned), especially
the sub-block has irregular shape (like a squid, spreading out all over to other blocks, for example, clock buffers..). I wonder if someone
can write a skill code to find floating vias in layout (floating vias means vias not connected to any nets or any instances).
I'm using cadence ic615.06.15.151
I am using Virtuoso XL, and I don't know the easy way to find floating vias in layout as you said. Let me explain the problem:
the sub block A is done by someone else, it is drc/lvs cleaned but it has some floating vias sitting alone somewhere in the block.
I am doing lvs on the top level which has A and B sub blocks( B also drc/lvs cleaned). Somehow, The floating vias in A short out two nets in B, and it took me a while to find out.
Another similar problem, both A and B are drc/lvs cleaned and they have psub2 layer cover it. But psub2 layer not 100% fully cover the block A ( it intersect one nmos transistor for example), as a result when I run lvs on the top level, I have ground lvs error.
It would be helpful if I have a skill code to find
1) Floating vias in layout
2) The intersection between two layer shape in layout, for example psub2 and pplus