Stats

  • Locked Locked
  • Replies 5
  • Subscribers 144
  • Views 15474
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

skill code to find floating vias in layout

pham777

when I do lvs verification, the one I hate most is the short causing by floating vias in sub block(sub block is lvs/drc cleaned), especially

the sub-block has irregular shape (like a squid, spreading out all over to other blocks, for example, clock buffers..). I wonder if someone

can write a skill code to find floating vias in layout (floating vias means vias not connected to any nets or any instances).

I'm using cadence ic615.06.15.151

Thanks,

ha

Parents

  • Hi Ted,

    If floating vias are just big enough, drc can not catch them. DRC also don't do anything with PSUB2 layer

    I am a layout guy, don't know much about writing SKILL. Could you be more specific about using dbGetTrueOverlaps in a procedure

    format.

    Thanks a lot,

    ha

Reply

  • Hi Ted,

    If floating vias are just big enough, drc can not catch them. DRC also don't do anything with PSUB2 layer

    I am a layout guy, don't know much about writing SKILL. Could you be more specific about using dbGetTrueOverlaps in a procedure

    format.

    Thanks a lot,

    ha

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.