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  3. skill code to find floating vias in layout

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skill code to find floating vias in layout

pham777
pham777 over 12 years ago

when I do lvs verification, the one I hate most is the short causing by floating vias in sub block(sub block is lvs/drc cleaned), especially

the sub-block has irregular shape (like a squid, spreading out all over to other blocks, for example, clock buffers..). I wonder if someone

can write a skill code to find floating vias in layout (floating vias means vias not connected to any nets or any instances).

I'm using cadence ic615.06.15.151

Thanks,

ha

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  • theopaone
    theopaone over 12 years ago

    You would have to have someone write a specific DRC deck to find the floating vias and look for the PSUB2 layer problem. These are checks that you should request from your CAD support.

    Sorry, I don't have access to write and test SKILL for outside customers, everything I write is owned by my clients. There are some other discussions on using dbGetTrueOverlaps with examples on this forum. You might also contact Cadence support because they have examples. You could also ask your CAD support to create the procedure.

    Ted

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  • theopaone
    theopaone over 12 years ago

    You would have to have someone write a specific DRC deck to find the floating vias and look for the PSUB2 layer problem. These are checks that you should request from your CAD support.

    Sorry, I don't have access to write and test SKILL for outside customers, everything I write is owned by my clients. There are some other discussions on using dbGetTrueOverlaps with examples on this forum. You might also contact Cadence support because they have examples. You could also ask your CAD support to create the procedure.

    Ted

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